UPD78F1142AF1-BA4-A Renesas Electronics America, UPD78F1142AF1-BA4-A Datasheet - Page 847

• Manufacturer Part Number: UPD78F1142AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1142AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt
functions
Key
interrupt
function
Standby
function
Function
MK0L, MK0H,
MK1L, MK1H,
MK2L, MK2H:
Interrupt mask
flag registers
PR00L, PR00H,
PR01L, PR01H,
PR02L, PR02H,
PR10L, PR10H,
PR11L, PR11H,
PR12L, PR12H:
Priority
specification flag
registers
EGP0, EGP1:
External
interrupt rising
edge enable
registers, EGN0,
EGN1: External
interrupt falling
edge enable
registers
Software
interrupt request
acknowledgment
BRK instruction
KRM: Key return
mode register
Details of
Function
−
Be sure to set bits 4 to 6 of MK1H and bits 1 to 7 of MK2H to 1.
Be sure to set bits 4 to 6 of PR01H and PR11H to 1.
Be sure to set bits 1 to 7 of PR02H and PR12H to 1.
Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Do not use the RETI instruction for restoring from the software interrupt.
The BRK instruction is not one of the above-listed interrupt request hold instructions.
However, the software interrupt activated by executing the BRK instruction causes
the IE flag to be cleared.
generated during execution of the BRK instruction, the interrupt request is not
acknowledged.
If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of
the corresponding pull-up resistor register 7 (PU7) to 1.
An interrupt will be generated if the target bit of the KRM register is set while a low
level is being input to the key interrupt input pin. To ignore this interrupt, set the KRM
register after disabling interrupt servicing by using the interrupt mask flag. Afterward,
clear the interrupt request flag and enable interrupt servicing after waiting for the key
interrupt input low-level width (250 ns or more).
The bits not used in the key interrupt mode can be used as normal ports.
The STOP mode can be used only when the CPU is operating on the main system
clock. The STOP mode cannot be set while the CPU operates with the subsystem
clock. The HALT mode can be used when the CPU is operating on either the main
system clock or the subsystem clock.
When shifting to the STOP mode, be sure to stop the peripheral hardware operation
operating with main system clock before executing STOP instruction.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
Therefore, even if a maskable interrupt request is
Cautions
p.585
p.587
p.589
p.593
p.597
p.599
p.599
p.599
p.600
p.600
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