UPD78F1142AF1-BA4-A Renesas Electronics America, UPD78F1142AF1-BA4-A Datasheet - Page 698

• Manufacturer Part Number: UPD78F1142AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1142AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
696
Instruction
8-bit
operation
Group
2.
3.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
Mnemonic
OR
XOR
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
When the program memory area is accessed.
Except r = A
register (CKC).
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum.
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, ES:!addr16
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, ES:!addr16
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
Operands
Note 3
Note 3
Table 26-5. Operation List (9/17)
CHAPTER 26 INSTRUCTION SET
Bytes
2
3
2
2
2
3
1
2
2
2
4
2
3
3
3
2
3
2
2
2
3
1
2
2
2
4
2
3
3
3
User’s Manual U17854EJ9V0UD
Note 1 Note 2
1
2
1
1
1
1
1
1
1
1
2
2
2
2
2
1
2
1
1
1
1
1
1
1
1
2
2
2
2
2
Clocks
−
−
−
−
−
4
4
4
4
4
5
5
5
5
5
−
−
−
−
−
4
4
4
4
4
5
5
5
5
5
A ← A ∨ byte
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
r ← r ∨ A
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A ← A ∨ (HL + byte)
A ← A ∨ (HL + B)
A ← A ∨ (HL + C)
A ← A ∨ (ES:addr16)
A ← A ∨ (ES:HL)
A ← A ∨ ((ES:HL) + byte)
A ← A ∨ ((ES:HL) + B)
A ← A ∨ ((ES:HL) + C)
A ← A ∨ byte
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
r ← r ∨ A
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A ← A ∨ (HL + byte)
A ← A ∨ (HL + B)
A ← A ∨ (HL + C)
A ← A ∨ (ES:addr16)
A ← A ∨ (ES:HL)
A ← A ∨ ((ES:HL) + byte)
A ← A ∨ ((ES:HL) + B)
A ← A ∨ ((ES:HL) + C)
CLK
) selected by the system clock control
Operation
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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