UPD78F1142AF1-BA4-A Renesas Electronics America, UPD78F1142AF1-BA4-A Datasheet - Page 237

• Manufacturer Part Number: UPD78F1142AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1142AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAU stop
Figure 6-50. Operation Procedure When Input Pulse Interval Measurement Function Is Used
n = 0 to 7, k = 0 to 6
Sets the TAU0EN bit of the PER0 register to 1.
Sets the TPS0 register.
Sets the TMR0n register (determines operation mode of
channel).
Sets TS0n bit to 1.
Set values of only the CIS0n1 and CIS0n0 bits of the
TMR0n register can be changed.
The TDR0n register can always be read.
The TCR0n register can always be read.
The TSR0n register can always be read.
Set values of TOM0n, TOL0n, TO0n, and TOE0n bits
cannot be changed.
The TT0n bit is set to 1.
The TAU0EN bit of the PER0 register is cleared to 0.
Determines clock frequencies of CK00 and CK01.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
The TT0n bit automatically returns to 0 because it is a
trigger bit.
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
Channel stops operating.
(Clock is supplied and some power is consumed.)
Counter (TCRn) counts up from 0000H. When the TI0k
pin input valid edge is detected, the count value is
transferred (captured) to TDR0n. At the same time,
TCR0n is cleared to 0000H, and the INTTM0n signal is
generated.
If an overflow occurs at this time, the OVF bit of the
TSR0n register is set; if an overflow does not occur, the
OVF bit is cleared.
After that, the above operation is repeated.
Power-off status
Power-on status. Each channel stops operating.
TE0n = 1, and count operation starts.
TE0n = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
TCR0n is cleared to 0000H at the count clock input.
When the MD0n0 bit of the TMR0n register is 1,
INTTM0n is generated.
TCR0n holds count value and stops.
The OVF bit of the TSR0n register is also held.
All circuits are initialized and SFR of each channel is
also initialized.
Hardware Status
235