UPD78F1142AF1-BA4-A Renesas Electronics America, UPD78F1142AF1-BA4-A Datasheet - Page 487

• Manufacturer Part Number: UPD78F1142AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1142AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
Note If the wait state is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the
Condition for clearing (COI0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (TRC0 = 0)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Cleared by WREL0 = 1
• When ALD0 changes from 0 to 1 (arbitration loss)
• Reset
<Master>
• When “1” is output to the first byte’s LSB (transfer
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer
<When not used for communication>
direction specification bit)
direction specification bit)
TRC0
COI0
0
1
0
1
ninth clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the
SDA0 line goes into a high-impedance state.
LREL0:
IICE0:
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0 line is set for high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Figure 12-7. Format of IIC Status Register 0 (IICS0) (2/3)
Bit 6 of IIC control register 0 (IICC0)
Bit 7 of IIC control register 0 (IICC0)
Note
CHAPTER 12 SERIAL INTERFACE IIC0
(wait cancel)
User’s Manual U17854EJ9V0UD
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (COI0 = 1)
• When the received address matches the local
Condition for setting (TRC0 = 1)
<Master>
• When a start condition is generated
• When “0” is output to the first byte’s LSB (transfer
<Slave>
• When “1” is input to the first byte’s LSB (transfer
address (slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
direction specification bit)
direction specification bit)
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