UPD78F1142AF1-BA4-A Renesas Electronics America, UPD78F1142AF1-BA4-A Datasheet - Page 866

• Manufacturer Part Number: UPD78F1142AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1142AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

864
4th edition
Edition
Addition of MD0n0 bit condition to titles in the following figures
• Figure 6-37 Example of Basic Timing of Operation as Interval Timer/Square
• Figure 6-45 Example of Basic Timing of Operation as Frequency Divider
• Figure 6-49 Example of Block Diagram of Operation as Input Pulse Interval
Change of description of 6.7.3 Operation as frequency divider
Change of description of 6.8.3 Operation as multiple PWM output function
Change of clear conditions of real-time counter
Change of description and Caution 1 in Figure 7-2 Format of Peripheral Enable
Register 0 (PER0)
Addition of Caution 2 to Figure 7-2 Format of Peripheral Enable Register 0
(PER0)
Addition of Caution to Figure 7-4 Format of Real-Time Counter Control Register
1 (RTCC1)
Addition of Caution to Figure 7-5 Format of Real-Time Counter Control Register 2
(RTCC2)
Change of Note 2 in 7.3 (5) Sub-count register (RSUBC)
Change of description of 7.3 (8) Hour count register (HOUR)
Change of bit name in Figure 7-17 Format of Alarm Week Register (ALARMWW)
Addition of Caution 2 to 10.3 (1) Peripheral enable register 0 (PER0)
Change of Table 10-2 A/D Conversion Time Selection
Addition of Caution 3 to 11.3 (1) Peripheral enable register 0 (PER0)
Change of Figure 11-7 Format of Serial Communication Operation Setting
Register mn (SCRmn)
Addition of description to 11.3 (13) Serial output level register m (SOLm)
Changes of bits 1 and 3 in Figure 11-16 Format of Serial Output Level Register m
(SOLm)
Changes of setting of (a) Serial output register m (SOm) and Note in Figure 11-66
Example of Contents of Registers for UART Transmission of UART (UART0,
UART1, UART2, UART3)
Change of Figure 11-89 Flowchart of Address Field Transmission
Change of Figure 11-92 Flowchart of Data Transmission
Addition of Caution 2 to 12.3 (1) Peripheral enable register 0 (PER0)
Change of description of 12.5.4 (2) Selection clock setting method on the slave
side
Addition of description to <1> and <3> in 14.4.1 Operation procedure
Addition of description to 14.5.5 Forced termination by software
Additions of description and Note to 14.6 (1) Priority of DMA
A
• Figure 17-4 HALT Mode Release by Reset
• Figure 17-6 STOP Mode Release by Interrupt Request Generation
• Figure 17-7 STOP Mode Release by Reset
Change of Figure 17-5 Operation Timing When STOP Mode Is Released
(When Unmasked Interrupt Request Is Generated)
Wave Output (MD0n0 = 1)
(MD0n0 = 1)
Measurement (MD0n0 = 0)
dditions of reset processing time and clock supply stop time to the following figures
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
Description
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER 10 A/D
CONVERTER
CHAPTER 11 SERIAL
ARRAY UNIT
CHAPTER 12 SERIAL
INTERFACE IIC0
CHAPTER 14 DMA
CONTROLLER
CHAPTER 17
STANDBY FUNCTION
Chapter
(2/15)