DS87C520-QNL+T&R Maxim Integrated Products, DS87C520-QNL+T&R Datasheet - Page 24

• Manufacturer Part Number: DS87C520-QNL+T&R
• Description: IC MCU EPROM/ROM 33MH IND 44PLCC
• Manufacturer: Maxim Integrated Products
• Series: 87Cr

Specifications of DS87C520-QNL+T&R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LCC, 44-PLCC
• Processor Series: DS87C520
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 44PLCC
• Device Core: 8051
• Family Name: 87C
• Maximum Speed: 33 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

will set an interrupt flag. Regardless of whether the user enables this interrupt, there are then 512 clocks
left until the reset flag is set. Software can enable the interrupt and reset individually. Note that the
Watchdog is a free running timer and does not require an enable.
There are 5 control bits in special function registers that affect the Watchdog Timer and two status flags
that report to the user. WDIF (WDCON.3) is the interrupt flag that is set at timer termination when there
are 512 clocks remaining until the reset flag is set. WTRF (WDCON.2) is the flag that is set when the
timer has completely timed out. This flag is normally associated with a CPU reset and allows software to
determine the reset source.
EWT (WDCON.1) is the enable for the Watchdog timer reset function. RWT (WDCON.0) is the bit that
software uses to restart the Watchdog Timer. Setting this bit restarts the timer for another full interval.
Application software must set this bit before the timeout. Both of these bits are protected by Timed
Access. As mentioned previously, WD1 and 0 (CKCON .7 and 6) select the timeout. The Reset
Watchdog Timer bit (WDCON.0) should be asserted prior to modifying the Watchdog Timer Mode
Select bits (WD1, WD0) to avoid corruption of the watchdog count. Finally, the user can enable the
Watchdog Interrupt using EWDI (EIE.4). The Special Function Register map is shown above.
INTERRUPTS
The DS87C520/DS83C520 provide 13 interrupt sources with three priority levels. The Power-Fail
Interrupt (PFI) has the highest priority. Software can assign high or low priority to other sources. All
interrupts that are new to the 8051 family, except for the PFI, have a lower natural priority than the
originals.
Table 8. Interrupt Sources and Priorities
SCON0
SCON1
NAME
WDTI
INT0
INT1
INT2
INT3
INT4
INT5
TF0
TF1
TF2
PFI
Power-Fail Interrupt
External Interrupt 0
Timer 0
External Interrupt 1
Timer 1
TI0 or RI0 from serial port 0
Timer 2
TI1 or RI1 from serial port 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog Timeout Interrupt
FUNCTION
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
24 of 43
VECTOR
0Bh
1Bh
2Bh
3Bh
4Bh
5Bh
33h
03h
13h
23h
43h
53h
63h
NATURAL
PRIORITY
10
11
12
13
1
2
3
4
5
6
7
8
9
8051/DALLAS
DALLAS
DALLAS
DALLAS
DALLAS
DALLAS
DALLAS
DALLAS
8051
8051
8051
8051
8051
8051