T89C51RD2-SLSIM Atmel, T89C51RD2-SLSIM Datasheet - Page 56

• Manufacturer Part Number: T89C51RD2-SLSIM
• Description: IC MICRO CTRL 64K FLASH 44PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of T89C51RD2-SLSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Default Values
Software Registers
56
T89C51RD2
Table 34. Program Lock bits
Note:
Note:
Note:
Note:
These security bits protect the code access through the parallel programming interface.
They are set by default to level 4. The code access through the ISP is still possible and
is controlled by the "software security bits" which are stored in the extra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must first be done.
This will set the HSB in its inactive state and will erase the Flash memory, including the
boot loader and the "Extra Flash Memory" (XAF). If needed, the 1K boot loader and the
XAF content must be programmed in the Flash; the code is provided by ATMEL Wire-
less and Microcontrollers (see section 8.7. ); the part reference can always be read
using Flash parallel programming modes.
The default value of the HSB provides parts ready to be programmed with ISP:
•
•
•
•
Several registers are used, in factory and by parallel programmers, to make copies of
hardware registers contents. These values are used by ATMEL Wireless and Microcon-
trollers ISP (see section 8.7. ).
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
•
•
Calls of API issued by the application software.
They are several software registers described in Table 35
Security
level
SB: Cleared to secure the content of the HSB.
BLJB: Cleared to force ISP operation.
BLLB: Clear to protect the default boot loader.
LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Commands issued by the parallel memory programmer.
Commands issued by the ISP software.
1
2
3
4
Program Lock Bits
U: unprogrammed or "one" level.
P: programmed or "zero" level.
X:do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
LB0
U
P
X
X
LB1
U
U
P
X
LB2
U
U
U
P
Protection Description
No program lock features enabled. MOVC instruction executed from
external program memory returns non encrypted data.
MOVC instruction executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and
latched on reset, and further parallel programming of the Flash is
disabled.ISP and software programming with API are still allowed.
Same as 2, also verify through parallel programming interface is
disabled.
Same as 3, also external execution is disabled.
4243G–8051–05/03