ATMEGA162-16PJ Atmel, ATMEGA162-16PJ Datasheet - Page 129

• Manufacturer Part Number: ATMEGA162-16PJ
• Description: IC MCU AVR 16K 5V 16MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16PJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

2513K–AVR–07/09
Table 54
mode.
Table 54. Compare Output Mode, Fast PWM
Note:
Table 55
rect or the phase and frequency correct, PWM mode.
Table 55. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
Note:
• Bit 3 – FOCnA: Force Output Compare for channel A
• Bit 2 – FOCnB: Force Output Compare for channel B
The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCRnA is written when operating in a PWM mode. When writing a logical one to the
FOCnA/FOCnB bit, an immediate Compare Match is forced on the Waveform Generation unit.
The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the
FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the
COMnx1:0 bits that determine the effect of the forced compare.
A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB bits are always read as zero.
COMnA1/
COMnA1/
COMnB1
COMnB1
0
0
1
1
0
0
1
1
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. In
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set.
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase cor-
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM
this case the Compare Match is ignored, but the set or clear is done at TOP.
Mode” on page 120.
“Phase Correct PWM Mode” on page 122.
COMnA0/
COMnA0
COMnB0
COMnB0
0
1
0
1
0
1
0
1
Description
Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 9 or 14: Toggle OCnA on Compare Match, OCnB
disconnected (normal port operation). For all other WGMn
settings, normal port operation, OCnA/OCnB disconnected.
Clear OCnA/OCnB on Compare Match when up-counting. Set
OCnA/OCnB on Compare Match when down-counting.
Set OCnA/OCnB on Compare Match when up-counting. Clear
OCnA/OCnB on Compare Match when down-counting.
Description
Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB
disconnected (normal port operation). For all other WGMn
settings, normal port operation, OCnA/OCnB disconnected.
Clear OCnA/OCnB on Compare Match, set OCnA/OCnB at TOP.
Set OCnA/OCnB on Compare Match, clear OCnA/OCnB at TOP.
for more details.
(1)
for more details.
ATmega162/V
See “Fast PWM
(1)
129
See