ATMEGA162-16PJ Atmel, ATMEGA162-16PJ Datasheet - Page 56

• Manufacturer Part Number: ATMEGA162-16PJ
• Description: IC MCU AVR 16K 5V 16MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16PJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

Timed Sequences
for Changing the
Configuration of
the Watchdog
Timer
Safety Level 0
Safety Level 1
Safety Level 2
56
ATmega162/V
The sequence for changing configuration differs slightly between the three safety levels. Sepa-
rate procedures are described for each level.
This mode is compatible with the Watchdog operation found in ATmega161. The Watchdog
Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restric-
tion. The Time-out period can be changed at any time without restriction. To disable an enabled
Watchdog Timer, the procedure described on
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to one without any restriction. A timed sequence is needed when changing the Watchdog Time-
out period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer,
and/or changing the Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
to WDE regardless of the previous value of the WDE bit.
desired, but with the WDCE bit cleared.
always is set, the WDE must be written to one to start the timed sequence.
but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
page 53
(WDE bit description) must be followed.
2513K–AVR–07/09