ATMEGA162-16PJ Atmel, ATMEGA162-16PJ Datasheet - Page 61

• Manufacturer Part Number: ATMEGA162-16PJ
• Description: IC MCU AVR 16K 5V 16MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16PJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

Moving Interrupts
Between Application
and Boot Space
General Interrupt
Control Register –
GICR
2513K–AVR–07/09
When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes and the IVSEL
bit in the GICR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash section is deter-
mined by the BOOTSZ Fuses. Refer to the section
Self-programming” on page 217
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
Bit
Read/Write
Initial Value
Address
.org 0x1C00
0x1C00
0x1C02
0x1C04
...
0x1C36
;
0x1C38
0x1C39
0x1C3A
0x1C3B
0x1C3C
0x1C3D
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
Write Self-programming” on page 217
Labels
....
RESET:
INT1
R/W
7
0
INT0
R/W
6
0
Code
jmp
jmp
jmp
..
jmp
ldi
out
ldi
out
sei
<instr>
RESET
EXT_INT0
EXT_INT1
SPM_RDY
r16,high(RAMEND) ; Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
INT2
R/W
5
0
for details. To avoid unintentional changes of Interrupt Vector
xxx
PCIE1
R/W
4
0
for details on Boot Lock bits.
PCIE0
R/W
Comments
; Reset handler
; IRQ0 Handler
; IRQ1 Handler
;
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
3
0
“Boot Loader Support – Read-While-Write
R
2
–
0
“Boot Loader Support – Read-While-
IVSEL
R/W
1
0
ATmega162/V
IVCE
R/W
0
0
GICR
61