Z8F6401VN020SC00TR Zilog, Z8F6401VN020SC00TR Datasheet - Page 125

• Manufacturer Part Number: Z8F6401VN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401VN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401VN020SC00T

Table 61. SPI Control Register (SPICTL)
PS017610-0404
RESET
FIELD
ADDR
BITS
R/W
SPI Control Register
IRQE
R/W
7
0
The SPI Control register configures the SPI for transmit and receive operations.
IRQE—Interrupt Request Enable
0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
STR—Start an SPI Interrupt Request
0 = No effect.
1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1. Setting this bit
forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by
software for a function similar to transmit buffer empty in a UART.
BIRQ—BRG Timer Interrupt Request
If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
PHASE—Phase Select
Sets the phase relationship of the data to the clock. Refer to the SPI Clock Phase and
Polarity Control section for more information on operation of the PHASE bit.
CLKPOL—Clock Polarity
0 = SCK idles Low (0).
1 = SCK idle High (1).
WOR—Wire-OR (Open-Drain) Mode Enabled
0 = SPI signal pins not configured for open-drain.
1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function.
This setting is typically used for multi-master and/or multi-slave configurations.
MMEN—SPI Master Mode Enable
0 = SPI configured in Slave mode.
1 = SPI configured in Master mode.
STR
R/W
6
0
BIRQ
R/W
5
0
PHASE
R/W
4
0
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
F61H
CLKPOL
R/W
3
0
WOR
R/W
2
0
Serial Peripheral Interface
MMEN
R/W
1
0
Z8 Encore!
SPIEN
R/W
0
0
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