Z8F6401VN020SC00TR Zilog, Z8F6401VN020SC00TR Datasheet - Page 44

• Manufacturer Part Number: Z8F6401VN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401VN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401VN020SC00T

Reset Sources
Table 8. Reset Sources and Resulting Reset Type
PS017610-0404
Operating Mode
Normal or Halt modes
Stop mode
System and Short Resets
During a System Reset, the Z8F640x family device is held in Reset for 514 cycles of the
Watch-Dog Timer oscillator followed by 16 cycles of the system clock (crystal oscillator).
A Short Reset differs from a System Reset only in the number of Watch-Dog Timer oscil-
lator cycles required to exit Reset. A Short Reset requires only 66 Watch-Dog Timer oscil-
lator cycles. Unless specifically stated otherwise, System Reset and Short Reset are
referred to collectively as Reset.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watch-Dog Timer oscillator continue to run. The system clock begins oper-
ating following the Watch-Dog Timer oscillator cycle count. The eZ8 CPU and on-chip
peripherals remain idle through the 16 cycles of the system clock.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses
that value into the Program Counter. Program execution begins at the Reset vector
address.
Table 8 lists the reset sources and type of Reset as a function of the Z8F640x family
device operating mode. The text following provides more detailed information on the indi-
vidual Reset sources. Please note that Power-On Reset / Voltage Brown-Out events always
have priority over all other possible reset sources to insure a full system reset occurs.
Reset Source
Power-On Reset / Voltage Brown-Out System Reset
Watch-Dog Timer time-out
when configured for Reset
RESET pin assertion
On-Chip Debugger initiated Reset
(OCDCTL[1] set to 1)
Power-On Reset / Voltage Brown-Out System Reset
RESET pin assertion
DBG pin driven Low
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Short Reset
Short Reset
System Reset except the On-Chip Debugger is
unaffected by the reset
System Reset
System Reset
Reset Type
Reset and Stop Mode Recovery
0002H
and
0003H
Z8 Encore!
and loads
®
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