Z8F6401VN020SC00TR Zilog, Z8F6401VN020SC00TR Datasheet - Page 129

• Manufacturer Part Number: Z8F6401VN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401VN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401VN020SC00T

I
Overview
Operation
PS017609-0803
2
C Controller
SDA and SCL Signals
The I
tocol. The I
(SDA) and a serial clock signal (SCL). Features of the I
•
•
•
•
The I
The I
master is supported. Arbitration between two masters must be accomplished in software.
I
•
•
•
•
I
bit first. SCL is the common clock for the I
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master (I
can become skewed by a slow slave device. During the high period of the clock, the slave
pulls the SCL signal Low to suspend the transaction. When the slave has released the line,
the I
2
2
C supports the following operations:
C sends all addresses, data and acknowledge signals over the SDA line, most-significant
Transmit and Receive Operation in Master mode
Maximum data rate of 400kbit/sec
7- and 10-bit Addressing Modes for Slaves
Unrestricted Number of Data Bytes Transmitted per Transfer
Master transmits to a 7-bit slave
Master transmits to a 10-bit slave
Master receives from a 7-bit slave
Master receives from a 10-bit slave
2
2
2
2
C Controller continues the transaction. All data is transferred in bytes and there is no
C Controller makes the Z8F640x family device bus-compatible with the I
C Controller in the Z8F640x family device does not operate in Slave mode.
C Controller operates in Master mode to transmit and receive data. Only a single
2
C Controller consists of two bidirectional bus lines—a serial data signal
2
C) is responsible for driving the SCL clock signal, although the clock signal
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
2
C Controller. When the SDA and SCL pin
2
C Controller include:
Z8 Encore!
I2C Controller
2
C
TM
pro-
®
111