Z8F6401VN020SC00TR Zilog, Z8F6401VN020SC00TR Datasheet - Page 131

• Manufacturer Part Number: Z8F6401VN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401VN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401VN020SC00T

PS017609-0803
S
Slave Address
2. The I
3. If the slave needs to service an interrupt, it pulls the SCL signal Low, which halts I
4. If there is no other data in the I
Figure 79 illustrates the data transfer format for a 7-bit addressed slave. Shaded regions
indicate data transferred from the I
data transferred from the slaves to the I
Figure 79. 7-Bit Addressed Slave Data Transfer Format
The data transfer format for a transmit operation on a 7-bit addressed slave is as follows:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing a 7-bit slave address followed by a 0
5. Software asserts the START bit of the I
6. The I
7. The I
8. After one bit of address has been shifted out by the SDA signal, the Transmit interrupt
9. Software responds by writing the contents of the data into the I
10. The I
11. The I
12. The I
13. The I
signal Low). If the slave pulls the SDA signal High (Not-Acknowledge), the I
Controller sends a Stop signal.
operation.
register is set by software, then the Stop signal is sent.
(write) to the I
register.
is asserted.
high period of SCL. The I
I
the Transmit interrupt is asserted.
2
C Data register.
2
2
2
2
2
2
2
2
C Controller waits for the slave to send an Acknowledge (by pulling the SDA
C interrupt asserts, because the I
C Controller sends the START condition to the I
C Controller loads the I
C Controller shifts the rest of the address and write bit out by the SDA signal.
C slave sends an acknowledge (by pulling the SDA signal low) during the next
C Controller loads the contents of the I
C Controller shifts the data out of via the SDA signal. After the first bit is sent,
W=0
2
C Data register.
A
2
C Controller sets the ACK bit in the I
Data
2
2
C Shift register with the contents of the I
2
C Controller to slaves and unshaded regions indicate
C Data register or the STOP bit in the I
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
2
C Controller.
2
2
C Control register.
C Control register to enable Transmit interrupts.
2
2
C Data register is empty
C Control register.
A
2
C Shift register with the contents of the
Data
2
C slave.
A
2
2
C Data register.
C Status register.
Data
2
Z8 Encore!
2
C Control
I2C Controller
C Data
2
A/A
C
2
P
C
®
113