MC68HC11E0CFN2

Manufacturer Part NumberMC68HC11E0CFN2
DescriptionIC MCU 2MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFN2 datasheet
 

Specifications of MC68HC11E0CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
M68HC11E Family
Data Sheet
M68HC11
Microcontrollers
M68HC11E/D
Rev. 5
6/2003
MOTOROLA.COM/SEMICONDUCTORS
For More Information On This Product,
Go to: www.freescale.com

MC68HC11E0CFN2 Summary of contents

  • Page 1

    ... Freescale Semiconductor, Inc. M68HC11 Microcontrollers MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com M68HC11E Family Data Sheet M68HC11E/D Rev. 5 6/2003 ...

  • Page 2

    ... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

  • Page 3

    ... Freescale Semiconductor, Inc. MC68HC11E Family Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document ...

  • Page 4

    ... Freescale Semiconductor, Inc. Revision History Revision Date Level 2.3.3.1 System Configuration Register description May, 2001 3.1 Added 10.21 EPROM Characteristics June, 2001 3.2 table December, 7.7.2 Serial Communications Control Register 1 3.3 2001 description corrected 10.7 MC68L11E9/E20 DC Electrical Characteristics include the MC68L11E20 10 ...

  • Page 5

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Section 2. Operating Modes and On-Chip Memory . . . . . . . . . . . . . . . 33 Section 3. Analog-to-Digital (A/D) Converter . . . . . . . . . . . . . . . . . . . . 63 Section 4. Central Processor Unit (CPU Section 5. Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Section 6. Parallel Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . 109 Section 7. Serial Communications Interface (SCI 117 Section 8 ...

  • Page 6

    ... Freescale Semiconductor, Inc. List of Sections Data Sheet 6 For More Information On This Product, List of Sections Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 7

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11E Family 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.7.1 1.4.8 1.4.9 1.4.10 1.4.10.1 1.4.10.2 1.4.10.3 1.4.10.4 1.4.10.5 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.1 2.2.2 2.2.3 2 ...

  • Page 8

    ... Freescale Semiconductor, Inc. Table of Contents 2.3.3 2.3.3.1 2.3.3.2 2.3.3.3 2.4 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4.1 2.4.2 2.4.3 2.5 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.5.1 2.5.1.1 2.5.1.2 2.5.1.3 2.5.1.4 2.5.1.5 2.5.1.6 2.5.2 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.2 Overview 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.3 A/D Converter Power-Up and Clock Select . . . . . . . . . . . . . . . . . . . . . . 66 3 ...

  • Page 9

    ... Freescale Semiconductor, Inc. 4.2.4 4.2.5 4.2.6 4.2.6.1 4.2.6.2 4.2.6.3 4.2.6.4 4.2.6.5 4.2.6.6 4.2.6.7 4.2.6.8 4.3 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.4 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.6 Instruction Set 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2.1 5.2.2 5.2.3 5.2.4 5 ...

  • Page 10

    ... Freescale Semiconductor, Inc. Table of Contents 5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.6 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.6.1 5.6.2 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.2 Port 109 6.3 Port 111 6.4 Port 111 6.5 Port 112 6.6 Port 113 6.7 Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6 ...

  • Page 11

    ... Freescale Semiconductor, Inc. 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.3 SPI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.4 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.5 SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.5.1 8.5.2 8.5.3 8.5.4 8.6 SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.7 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8.7.1 8.7.2 8 ...

  • Page 12

    ... Freescale Semiconductor, Inc. Table of Contents 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 10.2 Maximum Ratings for Standard 10.3 Functional Operating Range 166 10.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.6 Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 168 10.7 MC68L11E9/E20 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 169 10.8 MC68L11E9/E20 Supply Currents 10 ...

  • Page 13

    ... Freescale Semiconductor, Inc. 11.9 56-Pin Dual in-Line Package (Case 859 202 11.10 48-Pin Plastic DIP (Case 767 202 A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 A.2 Motorola M68HC11 E-Series Development Tools . . . . . . . . . . . . . . . . 203 A.3 EVS — Evaluation System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 A.4 Motorola Modular Development System (MMDS11 204 A.5 SPGMR11 — ...

  • Page 14

    ... Freescale Semiconductor, Inc. Table of Contents Data Sheet 14 For More Information On This Product, Table of Contents Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 15

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 1.1 Introduction This document contains a detailed description of the M68HC11 E series of 8-bit microcontroller units (MCUs). These MCUs all combine the M68HC11 central processor unit (CPU) with high-performance, on-chip peripherals. The E series is comprised of many devices with various configurations of: • ...

  • Page 16

    ... Freescale Semiconductor, Inc. General Description • 16-bit timer system: – – – • 8-bit pulse accumulator • Real-time interrupt circuit • Computer operating properly (COP) watchdog system • 38 general-purpose input/output (I/O) pins: – – – • Several packaging options: – – ...

  • Page 17

    ... Freescale Semiconductor, Inc. MODA/ MODB/ LIR V XTAL EXTAL E STBY OSC MODE CONTROL CLOCK LOGIC TIMER SYSTEM BUS EXPANSION ADDRESS PORT A PORT applies only to devices with EPROM/OTPROM. PPE Figure 1-1. M68HC11 E-Series Block Diagram M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product, ...

  • Page 18

    ... Freescale Semiconductor, Inc. General Description 1.4 Pin Descriptions M68HC11 E-series MCUs are available packaged in: • 52-pin plastic-leaded chip carrier (PLCC) • 52-pin windowed ceramic leaded chip carrier (CLCC) • 52-pin plastic thin quad flat pack (TQFP) • 64-pin quad flat pack (QFP) • ...

  • Page 19

    ... Freescale Semiconductor, Inc. PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 1. V M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product, 1 PA0/IC3 M68HC11 E SERIES PE0/AN0 13 PE4/AN4 14 PE1/AN1 15 PE5/AN5 16 applies only to devices with EPROM/OTPROM. PPE Figure 1-3. Pin Assignments for 64-Pin QFP General Description Go to: www ...

  • Page 20

    ... Freescale Semiconductor, Inc. General Description Data Sheet 20 For More Information On This Product, 1 PA0/IC3 PB7/ADDR15 2 PB6/ADDR14 3 PB5/ADDR13 4 PB4/ADDR12 5 PB3/ADDR11 6 M68HC11 E SERIES PB2/ADDR10 7 PB1/ADDR9 8 PB0/ADDR8 9 PE0/AN0 10 11 PE4/AN4 12 PE1/AN1 PE5/AN5 applies only to devices with EPROM/OTPROM. PPE Figure 1-4. Pin Assignments for 52-Pin TQFP General Description Go to: www ...

  • Page 21

    ... Freescale Semiconductor, Inc. M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product MODB/V STBY 2 MODA/LIR 3 STRA/ STRB/R/W 6 EXTAL 7 XTAL 8 PC0/ADDR0/DATA0 9 PC1/ADDR1/DATA1 10 PC2/ADDR2/DATA2 11 PC3/ADDR3/DATA3 12 PC4/ADDR4/DATA4 13 PC5/ADDR5/DATA5 14 PC6/ADDR6/DATA6 15 M68HC11 E SERIES PC7/ADDR7/DATA7 16 RESET 17 * XIRQ/V PPE 18 IRQ 19 PD0/RxD PD1/TxD 22 PD2/MISO 23 PD3/MOSI 24 PD4/SCK 25 PD5/ applies only to devices with EPROM/OTPROM. ...

  • Page 22

    ... Freescale Semiconductor, Inc. General Description Figure 1-6. Pin Assignments for 48-Pin DIP (MC68HC811E2) Data Sheet 22 For More Information On This Product, PA7/PAI/OC1 1 PA6/OC2/OC1 2 PA5/OC3/OC1 3 PA4/OC4/OC1 4 PA3/OC5/IC4/OC1 5 PA2/IC1 6 PA1/IC2 7 PA0/IC3 8 PB7/ADDR15 9 PB6/ADDR14 10 PB5/ADDR13 11 PB4/ADDR12 MC68HC811E2 12 PB3/ADDR11 13 PB2/ADDR10 14 PB1/ADDR9 15 PB0/ADDR8 16 PE0/AN0 17 PE1/AN1 18 PE2/AN2 19 PE3/AN3 ...

  • Page 23

    ... Freescale Semiconductor, Inc. 1.4.1 V and Power is supplied to the MCU through V is ground. The MCU operates from a single 5-volt (nominal) power supply. Low-voltage devices in the E series operate at 3.0–5.5 volts. Very fast signal transitions occur on the MCU pins. The short rise and fall times place high, short duration current demands on the power supply ...

  • Page 24

    ... Freescale Semiconductor, Inc. General Description 1.4.2 RESET A bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly (COP) watchdog circuit. The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E-clock cycles after a reset has occurred ...

  • Page 25

    ... Freescale Semiconductor, Inc. CAUTION: In all cases, use caution around the oscillator pins. Load capacitances shown in the oscillator circuit are specified by the crystal manufacturer and should include all stray layout capacitances. Figure 1-9. Common Parallel Resonant Crystal Connections 1.4.4 E-Clock Output ( the output connection for the internally generated E clock. The signal from E is used as a timing reference ...

  • Page 26

    ... Freescale Semiconductor, Inc. General Description 1.4.6 Non-Maskable Interrupt (XIRQ/V The XIRQ input provides a means of requesting a non-maskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the XIRQ input ...

  • Page 27

    ... Freescale Semiconductor, Inc. The V STBY When the voltage on this pin is more than one MOS threshold (about 0.7 volts) above the V from this signal rather than the V without V DD removed and must remain low until V 1.4.7.1 V and These two inputs provide the reference voltages for the analog-to-digital (A/D) converter circuitry: • ...

  • Page 28

    ... Freescale Semiconductor, Inc. General Description 1.4.10 Port Signals Port pins have different functions in different operating modes. Pin functions for port A, port D, and port E are independent of operating modes. Port B and port C, however, are affected by operating mode. Port B provides eight general-purpose output signals in single-chip operating modes. When the microcontroller is in expanded multiplexed operating mode, port B pins are the eight high-order address lines ...

  • Page 29

    ... Freescale Semiconductor, Inc. Port/Bit PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 M68HC11E Family — ...

  • Page 30

    ... Freescale Semiconductor, Inc. General Description 1.4.10.2 Port B During single-chip operating modes, all port B pins are general-purpose output pins. During MCU reads of this port, the level sensed at the input side of the port B output drivers is read. Port B can also be used in simple strobed output mode. In this mode, an output pulse appears at the STRB signal each time data is written to port B ...

  • Page 31

    ... Freescale Semiconductor, Inc. 1.4.10.4 Port D Pins PD5–PD0 can be used for general-purpose I/O signals. These pins alternately serve as the serial communication interface (SCI) and serial peripheral interface (SPI) signals when those subsystems are enabled. • PD0 is the receive data input (RxD) signal for the SCI. ...

  • Page 32

    ... Freescale Semiconductor, Inc. General Description Data Sheet 32 For More Information On This Product, General Description Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 33

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 2.1 Introduction This section contains information about the operating modes and the on-chip memory for M68HC11 E-series MCUs. Except for a few minor differences, operation is identical for all devices in the E series. Differences are noted where necessary ...

  • Page 34

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory The expansion bus is made up of ports B and C, and control signals AS (address strobe) and R/W (read/write). R/W and AS allow the low-order address and the 8-bit data bus to be multiplexed on the same pins. During the first half of each bus cycle address information is present ...

  • Page 35

    ... Freescale Semiconductor, Inc. configuration (CONFIG) register, programming calibration data into electrically erasable, programmable read-only memory (EEPROM), and supporting emulation and debugging during development. 2.2.4 Bootstrap Mode When the MCU is reset in special bootstrap mode, a small on-chip read-only memory (ROM) is enabled at address $BF00–$BFFF. The ROM contains a bootloader program and a special set of interrupt and reset vectors ...

  • Page 36

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory $0000 EXT $1000 $B600 EXT $D000 $FFFF EXPANDED BOOTSTRAP Figure 2-2. Memory Map for MC68HC11E0 $0000 EXT $1000 EXT $B600 EXT $D000 $FFFF EXPANDED BOOTSTRAP Figure 2-3. Memory Map for MC68HC11E1 Data Sheet ...

  • Page 37

    ... Freescale Semiconductor, Inc. $0000 EXT $1000 EXT $B600 EXT $D000 $FFFF SINGLE EXPANDED CHIP Figure 2-4. Memory Map for MC68HC(7)11E9 $0000 EXT $1000 EXT $9000 EXT $B600 EXT $D000 $FFFF SINGLE EXPANDED CHIP * 20 Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each. ...

  • Page 38

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory $0000 EXT $1000 EXT $F800 $FFFF SINGLE EXPANDED CHIP Figure 2-6. Memory Map for MC68HC811E2 Addr. Register Name Port A Data Register $1000 (PORTA) See page 110. $1001 Reserved Parallel I/O Control Register $1002 (PIOC) See page 115 ...

  • Page 39

    ... Freescale Semiconductor, Inc. Addr. Register Name Port C Latched Register $1005 (PORTCL) See page 112. Reset: $1006 Reserved Port C Data Direction Register $1007 (DDRC) See page 112. Reset: Port D Data Register $1008 (PORTD) See page 112. Reset: Port D Data Direction Register $1009 (DDRD) See page 113 ...

  • Page 40

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Addr. Register Name Timer Input Capture 2 Register $1012 High (TIC2H) See page 147. TImer Input Capture 2 Register $1013 Low (TIC2L) See page 147. Timer Input Capture 3 Register $1014 High (TIC3H) See page 147. ...

  • Page 41

    ... Freescale Semiconductor, Inc. Addr. Register Name Timer Input Capture 4/Output $101E Compare 5 Register High (TI4/O5) See page 148. Reset: Timer Input Capture 4/Output $101F Compare 5 Register Low (TI4/O5) See page 148. Reset: Timer Control Register 1 $1020 (TCTL1) See page 153. Reset: ...

  • Page 42

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Addr. Register Name Serial Peripheral Data I/O $102A Register (SPDR) See page 140. Baud Rate Register $102B (BAUD) See page 126. Serial Communications Control $102C Register 1 (SCCR1) See page 123. Serial Communications Control ...

  • Page 43

    ... Freescale Semiconductor, Inc. Addr. Register Name EPROM Programming Control (1) $1036 Register (EPROG) See page 59. Reset: $1037 Reserved 1. MC68HC711E20 only $1038 Reserved System Configuration Options $1039 Register (OPTION) See page 51. Reset: Arm/Reset COP Timer Circuitry $103A Register (COPRST) See page 91. Reset: EPROM and EEPROM ...

  • Page 44

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 2.3.1 RAM and Input/Output Mapping Hardware priority is built into RAM and I/O mapping. Registers have priority over RAM and RAM has priority over ROM. When a lower priority resource is mapped at the same location as a higher priority resource, a read/write of a location results in a read/write of the higher priority resource only ...

  • Page 45

    ... Freescale Semiconductor, Inc. In expanded modes, the ROM/EPROM/OTPROM (if present) is enabled out of reset and located at the top of the memory map if the ROMON bit in the CONFIG register is set. ROM or EPROM is enabled out of reset in single-chip and bootstrap modes, regardless of the state of ROMON. For devices with 512 bytes of EEPROM, the EEPROM is located at $B600–$B7FF and has the same read cycle time as the internal ROM ...

  • Page 46

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory A normal mode is selected when MODB is logic 1 during reset. One of three reset vectors is fetched from address $FFFA–$FFFF, and program execution begins from the address indicated by this vector. If MODB is logic 0 during reset, the special mode reset vector is fetched from addresses $BFFA– ...

  • Page 47

    ... Freescale Semiconductor, Inc. IRV(NE) — Internal Read Visibility (Not E) Bit IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV off. In special test mode, IRVNE is reset all other modes, IRVNE is reset to 0. For the MC68HC811E2, this bit is IRV and only controls the internal read visibility function. ...

  • Page 48

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 2.3.3.1 System Configuration Register The system configuration register (CONFIG) consists of an EEPROM byte and static latches that control the startup configuration of the MCU. The contents of the EEPROM byte are transferred into static working latches during reset sequences. ...

  • Page 49

    ... Freescale Semiconductor, Inc. Address: Read: Write: Resets: Single chip: Bootstrap: Expanded: Test: U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register. Figure 2-11. MC68HC811E2 System Configuration Register (CONFIG) EE[3:0] — ...

  • Page 50

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory NOSEC — Security Disable Bit NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If the security mask option is omitted NOSEC always reads 1. The enhanced security feature is available in the MC68S711E9 MCU. The enhancement to the standard security feature protects the EPROM as well as RAM and EEPROM ...

  • Page 51

    ... Freescale Semiconductor, Inc. REG[3:0] — 64-Byte Register Block Position These four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal registers. The register block, positioned at the beginning of any 4-Kbyte page in the memory map, is initialized to address $1000 out of reset. Refer to Table 2-4 ...

  • Page 52

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory ADPU — Analog-to-Digital Converter Power-Up Bit Refer to CSEL — Clock Select Bit Selects alternate clock source for on-chip EEPROM charge pump. Refer to 2.5.1 EEPROM and CONFIG Programming and Erasure on EEPROM use. CSEL also selects the clock source for the A/D converter, a function discussed in Section 3 ...

  • Page 53

    ... Freescale Semiconductor, Inc. Using the on-chip EPROM/OTPROM programming feature requires an external 12-volt nominal power supply (V the EPROM/OTPROM programming register (PPROG). PPROG is the combined EPROM/OTPROM and EEPROM programming register on all devices with EPROM/OTPROM except the MC68HC711E20. For the MC68HC711E20, there is a separate register for EPROM/OTPROM programming called the EPROG register ...

  • Page 54

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 2.4.2 Programming the EPROM with Downloaded Data When using this method, the EPROM is programmed by software while in the special test or bootstrap modes. User-developed software can be uploaded through the SCI or a ROM-resident EPROM programming utility can be used. The ...

  • Page 55

    ... Freescale Semiconductor, Inc. ELAT — EPROM/OTPROM Latch Control Bit When ELAT = 1, writes to EPROM cause address and data to be latched and the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can be written any time except when EPGM = 1; then the write to ELAT is disabled. ...

  • Page 56

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Bit 6 — Unimplemented Always reads 0 ELAT — EPROM/OTPROM Latch Control Bit When ELAT = 1, writes to EPROM cause address and data to be latched and the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can be written any time except when PGM = 1 ...

  • Page 57

    ... Freescale Semiconductor, Inc. 2.5 EEPROM Some E-series devices contain 512 bytes of on-chip EEPROM. The MC68HC811E2 contains 2048 bytes of EEPROM with selectable base address. All E-series devices contain the EEPROM-based CONFIG register. 2.5.1 EEPROM and CONFIG Programming and Erasure The erased state of an EEPROM bit is 1. During a read operation, bit lines are precharged to 1 ...

  • Page 58

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Address: $1035 Read: Write: Reset: Bits [7:5] — Unimplemented Always read 0 PTCON — Protect CONFIG Register Bit 0 = CONFIG register can be programmed or erased normally CONFIG register cannot be programmed or erased. BPRT[3:0] — Block Protect Bits for EEPROM When set, these bits protect a block of EEPROM from being programmed or electronically erased ...

  • Page 59

    ... Freescale Semiconductor, Inc. Address: $103B Read: Write: Reset: 1. MC68HC711E9 only ODD — Program Odd Rows in Half of EEPROM (Test) Bit EVEN — Program Even Rows in Half of EEPROM (Test) Bit ELAT — EPROM/OTPROM Latch Control Bit For the MC68HC711E9, EPGM enables the high voltage necessary for both EPROM/OTPROM and EEPROM programming ...

  • Page 60

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory EPGM — EPROM/OTPROM/EEPROM Programming Voltage Enable Bit 0 = Programming voltage to EEPROM array switched off 1 = Programming voltage to EEPROM array switched on During EEPROM programming, the ROW and BYTE bits of PPROG are not used. If the frequency of the E clock is 1 MHz or less, set the CSEL bit in the OPTION register ...

  • Page 61

    ... Freescale Semiconductor, Inc. 2.5.1.5 EEPROM Byte Erase This is an example of how to erase a single byte of EEPROM. BYTEE 2.5.1.6 CONFIG Register Programming Because the CONFIG register is implemented with EEPROM cells, use EEPROM procedures to erase and program this register. The procedure for programming is the same as for programming a byte in the EEPROM array, except that the CONFIG register address is used ...

  • Page 62

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory For further information, these engineering bulletins have been included at the back of this data book: • EB183 — with PCbug11 on the M68HC711E9PGMR • EB188 — PCbug11 on the M68HC711E9PGMR Data Sheet 62 For More Information On This Product, ...

  • Page 63

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 3.1 Introduction The analog-to-digital (A/D) system, a successive approximation converter, uses an all-capacitive charge redistribution technique to convert analog signals to digital values. 3.2 Overview The A/D system is an 8-channel, 8-bit, multiplexed-input converter. The converter does not require external sample and hold circuits because of the type of charge redistribution technique used ...

  • Page 64

    ... Freescale Semiconductor, Inc. Analog-to-Digital (A/D) Converter PE0 AN0 PE1 AN1 PE2 AN2 PE3 AN3 ANALOG MUX PE4 AN4 PE5 AN5 PE6 AN6 PE7 AN7 ADR1 A/D RESULT 1 Figure 3-1. A/D Converter Block Diagram ANALOG INPUT PIN + ~20 V – ~0.7 V < INPUT ...

  • Page 65

    ... Freescale Semiconductor, Inc. 3.2.2 Analog Converter Conversion of an analog input selected by the multiplexer occurs in this block. It contains a digital-to-analog capacitor (DAC) array, a comparator, and a successive approximation register (SAR). Each conversion is a sequence of eight comparison operations, beginning with the most significant bit (MSB). Each comparison determines the value of a bit in the successive approximation register ...

  • Page 66

    ... Freescale Semiconductor, Inc. Analog-to-Digital (A/D) Converter 3.2.6 Conversion Sequence A/D converter operations are performed in sequences of four conversions each. A conversion sequence can repeat continuously or stop after one iteration. The conversion complete flag (CCF) is set after the fourth conversion in a sequence to show the availability of data in the result registers. ...

  • Page 67

    ... Freescale Semiconductor, Inc. ADPU — A/D Power-Up Bit 0 = A/D powered down 1 = A/D powered up CSEL — Clock Select Bit 0 = A/D and EEPROM use system E clock A/D and EEPROM use internal RC clock. IRQE — Configure IRQ for Edge-Sensitive Only Operation Refer to DLY — Enable Oscillator Startup Delay Bit ...

  • Page 68

    ... Freescale Semiconductor, Inc. Analog-to-Digital (A/D) Converter 3.6 Single-Channel Operation The two types of single-channel operation are: 1. When SCAN = 0, the single selected channel is converted four consecutive times. The first result is stored in A/D result register 1 (ADR1), and the fourth result is stored in ADR4. After the fourth conversion is complete, all conversion activity is halted until a new conversion command is written to the ADCTL register ...

  • Page 69

    ... Freescale Semiconductor, Inc. 3.8 Operation in Stop and Wait Modes If a conversion sequence is in progress when either the stop or wait mode is entered, the conversion of the current channel is suspended. When the MCU resumes normal operation, that channel is resampled and the conversion sequence is resumed. As the MCU exits wait mode, the A/D circuits are stable and valid results can be obtained on the first conversion ...

  • Page 70

    ... Freescale Semiconductor, Inc. Analog-to-Digital (A/D) Converter system is configured to perform a conversion on each of four channels where each result register corresponds to one channel. NOTE: When the multiple-channel continuous scan mode is used, extra care is needed in the design of circuitry driving the A/D inputs. The charge on the capacitive DAC array before the sample time is related to the voltage on the previously converted channel ...

  • Page 71

    ... Freescale Semiconductor, Inc. 3.10 A/D Converter Result Registers These read-only registers hold an 8-bit conversion result. Writes to these registers have no effect. Data in the A/D converter result registers is valid when the CCF flag in the ADCTL register is set, indicating a conversion sequence is complete. If conversion results are needed sooner, refer to conversion sequence diagram ...

  • Page 72

    ... Freescale Semiconductor, Inc. Analog-to-Digital (A/D) Converter Data Sheet 72 For More Information On This Product, Analog-to-Digital (A/D) Converter Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 73

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 4.1 Introduction Features of the M68HC11 Family include: • Central processor unit (CPU) architecture • Data types • Addressing modes • Instruction set • Special operations such as subroutine calls and interrupts The CPU is designed to treat all peripheral, input/output (I/O), and memory locations identically as addresses in the 64-Kbyte memory map ...

  • Page 74

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU 4.2.1 Accumulators A, B, and D Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumulator D. Although most instructions can use accumulators interchangeably, these exceptions apply: • ...

  • Page 75

    ... Freescale Semiconductor, Inc. 4.2.2 Index Register X (IX) The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. The IX register can also be used as a counter temporary storage register. 4.2.3 Index Register Y (IY) The 16-bit IY register performs an indexed mode function similar to that of the IX register ...

  • Page 76

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) JSR, JUMP TO SUBROUTINE MAIN PROGRAM PC $9D = JSR DIRECT dd NEXT MAIN INSTR. RTN MAIN PROGRAM PC $AD = JSR INDEXED NEXT MAIN INSTR. RTN MAIN PROGRAM PC $18 = PRE INDEXED, Y $AD = JSR ff RTN NEXT MAIN INSTR. MAIN PROGRAM ...

  • Page 77

    ... Freescale Semiconductor, Inc. 4.2.6 Condition Code Register (CCR) This 8-bit register contains: • Five condition code indicators ( and H), • Two interrupt masking bits (IRQ and XIRQ) • A stop disable bit (S) In the M68HC11 CPU, condition codes are updated automatically by most instructions. For example, load accumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the N, Z, and V condition code flags ...

  • Page 78

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) operation of the CPU continues uninterrupted until the I bit is cleared. After any reset, the I bit is set by default and can only be cleared by a software instruction. When an interrupt is recognized, the I bit is set after the registers are stacked, but before the interrupt vector is fetched ...

  • Page 79

    ... Freescale Semiconductor, Inc. A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. Because the M68HC11 is an 8-bit CPU, there are no special requirements for alignment of instructions or operands. ...

  • Page 80

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 4.5.2 Direct In the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00–$FF are thus accessed directly, using 2-byte instructions. Execution time is reduced by eliminating the additional memory access required for the high-order address byte ...

  • Page 81

    ... Freescale Semiconductor, Inc. Table 4-2. Instruction Set (Sheet Mnemonic Operation Description ⇒ A ABA Add Accumulators ⇒ IX ABX Add ( ⇒ IY ABY Add ⇒ A ADCA (opr) Add with Carry ⇒ B ADCB (opr) Add with Carry ⇒ A ADDA (opr) Add Memory ⇒ B ADDB (opr) ...

  • Page 82

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 4-2. Instruction Set (Sheet Mnemonic Operation Description BEQ (rel) Branch if = Zero ? Branch if ∆ Zero ? N ⊕ BGE (rel ⊕ BGT (rel) Branch if > Zero BHI (rel) Branch Higher BHS (rel) Branch Higher or Same BITA (opr) Bit(s) Test A A • ...

  • Page 83

    ... Freescale Semiconductor, Inc. Table 4-2. Instruction Set (Sheet Mnemonic Operation Description CMPA (opr) Compare – M Memory CMPB (opr) Compare – M Memory $FF – M ⇒ M COM (opr) Ones Complement Memory Byte $FF – A ⇒ A COMA Ones Complement A $FF – B ⇒ B COMB Ones Complement B CPD (opr) Compare – ...

  • Page 84

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 4-2. Instruction Set (Sheet Mnemonic Operation Description ⇒ M INC (opr) Increment Memory Byte ⇒ A INCA Increment Accumulator ⇒ B INCB Increment Accumulator ⇒ SP INS Increment Stack Pointer ⇒ IX INX Increment Index Register ⇒ IY INY ...

  • Page 85

    ... Freescale Semiconductor, Inc. Table 4-2. Instruction Set (Sheet Mnemonic Operation Description LSR (opr) Logical Shift Right LSRA Logical Shift Right LSRB Logical Shift Right LSRD Logical Shift Right Double ∗ B ⇒ D MUL Multiply – M ⇒ M NEG (opr) Two’s Complement Memory Byte 0 – ...

  • Page 86

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 4-2. Instruction Set (Sheet Mnemonic Operation Description RORA Rotate Right RORB Rotate Right RTI Return from See Figure 3–2 Interrupt RTS Return from See Figure 3–2 Subroutine A – B ⇒ A SBA Subtract B from A A – M – C ⇒ A ...

  • Page 87

    ... Freescale Semiconductor, Inc. Table 4-2. Instruction Set (Sheet Mnemonic Operation Description SWI Software See Figure 3–2 Interrupt A ⇒ B TAB Transfer ⇒ CCR TAP Transfer Register B ⇒ A TBA Transfer TEST TEST (Only in Address Bus Counts Test Modes) CCR ⇒ A TPA Transfer CC Register to A ...

  • Page 88

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Data Sheet 88 For More Information On This Product, Central Processor Unit (CPU) Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 89

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 5.1 Introduction Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset immediately stops execution of the current instruction and forces the program counter to a known starting address ...

  • Page 90

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.2.2 External Reset (RESET) The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E-clock cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is driven low by an internal device for four E-clock cycles, then released ...

  • Page 91

    ... Freescale Semiconductor, Inc. Address Read: Write: Reset: Figure 5-1. Arm/Reset COP Timer Circuitry Register (COPRST) Complete this 2-step reset sequence to service the COP timer: 1. Write $55 to COPRST to arm the COP timer clearing mechanism. 2. Write $AA to COPRST to clear the COP timer. Performing instructions between these two steps is possible as long as both steps are completed in the correct sequence before the timer times out ...

  • Page 92

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.2.5 System Configuration Options Register Address: Read: Write: Reset: 1. Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes Figure 5-2. System Configuration Options Register (OPTION) ADPU — Analog-to-Digital Converter Power-Up Bit Refer to CSEL — ...

  • Page 93

    ... Freescale Semiconductor, Inc. 5.2.6 Configuration Control Register Address: Read: Write: Reset: EE[3:0] — EEPROM Mapping Bits EE[3:0] apply only to MC68HC811E2. Refer to and On-Chip NOSEC — Security Mode Disable Bit Refer to NOCOP — COP System Disable Bit 0 = COP enabled (forces reset on timeout COP disabled (does not force reset on timeout) ROMON — ...

  • Page 94

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.3.1 Central Processor Unit (CPU) After reset, the central processor unit (CPU) fetches the restart vector from the appropriate address during the first three cycles and begins executing instructions. The stack pointer and other CPU registers are indeterminate immediately after reset ...

  • Page 95

    ... Freescale Semiconductor, Inc. 5.3.6 Computer Operating Properly (COP) The COP watchdog system is enabled if the NOCOP control bit in the CONFIG register is cleared and disabled if NOCOP is set. The COP rate is set for the shortest duration timeout. 5.3.7 Serial Communications Interface (SCI) The reset condition of the SCI system is independent of the operating mode. At reset, the SCI baud rate control register (BAUD) is initialized to $04 ...

  • Page 96

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.4 Reset and Interrupt Priority Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced first when simultaneous requests occur. Any maskable interrupt can be given priority over other maskable interrupts. The first six interrupt sources are not maskable. The priority arrangement for these sources is: 1 ...

  • Page 97

    ... Freescale Semiconductor, Inc. 5.4.1 Highest Priority Interrupt and Miscellaneous Register Address: Read: Write: Reset: Single chip: Expanded: Bootstrap: Special test: 1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the RESET pin rising edge. Refer to RBOOT — Read Bootstrap ROM Bit Has meaning only when the SMOD bit (bootstrap mode or special test mode) ...

  • Page 98

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.5 Interrupts The MCU has 18 interrupt vectors that support 22 interrupt sources. The 15 maskable interrupts are generated by on-chip peripheral systems. These interrupts are recognized when the global interrupt mask bit (I) in the condition code register (CCR) is clear. The three non-maskable interrupt sources are illegal opcode trap, software interrupt, and XIRQ pin ...

  • Page 99

    ... Freescale Semiconductor, Inc. Vector Address FFC0, C1 – FFD4, D5 Reserved FFD6, D7 FFD8, D9 FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB FFEC, ED FFEE, EF FFF0, F1 FFF2, F3 FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product, Table 5-4. Interrupt and Reset Vector Assignments ...

  • Page 100

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.5.1 Interrupt Recognition and Register Stacking An interrupt can be recognized at any time after it is enabled by its local mask, if any, and by the global mask bit in the CCR. Once an interrupt source is recognized, the CPU responds at the completion of the instruction being executed. Interrupt latency varies according to the number of cycles required to complete the current instruction ...

  • Page 101

    ... Freescale Semiconductor, Inc. stacking the CCR. A return-from-interrupt instruction restores the X and I bits to their pre-interrupt request state. 5.5.3 Illegal Opcode Trap Because not all possible opcodes or opcode sequences are defined, the MCU includes an illegal opcode detection circuit, which generates an interrupt request. When an illegal opcode is detected and the interrupt is recognized, the current value of the program counter is stacked ...

  • Page 102

    ... Freescale Semiconductor, Inc. Resets and Interrupts HIGHEST PRIORITY POWER-ON RESET (POR) DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) Figure 5-5. Processing Flow Out of Reset (Sheet Data Sheet 102 For More Information On This Product, EXTERNAL RESET CLOCK MONITOR FAIL ...

  • Page 103

    ... Freescale Semiconductor, Inc. STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF8, $FFF9 STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF6, $FFF7 Figure 5-5. Processing Flow Out of Reset (Sheet M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product, ...

  • Page 104

    ... Freescale Semiconductor, Inc. Resets and Interrupts BEGIN X BIT IN CCR SET ? NO HIGHEST PRIORITY INTERRUPT ? NO IRQ ? NO RTII = IC1I = IC2I = IC3I = OC1I = Figure 5-6. Interrupt Priority Resolution (Sheet Data Sheet 104 For More Information On This Product, YES YES XIRQ PIN SET X BIT IN CCR LOW ? ...

  • Page 105

    ... Freescale Semiconductor, Inc OC2I = OC3I = OC4I = I4/O5I = TOI = PAOVI = PAII = SPIE = 1? N SCI Y INTERRUPT? SEE FIGURE 5–3 N Figure 5-6. Interrupt Priority Resolution (Sheet M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product, Y FLAG FETCH VECTOR OC2F = 1? $FFE6, $FFE7 N Y FLAG ...

  • Page 106

    ... Freescale Semiconductor, Inc. Resets and Interrupts BEGIN FLAG Y RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 5-7. Interrupt Source Resolution Within SCI Data Sheet 106 For More Information On This Product, Y RIE = TIE = TCIE = ILIE = Resets and Interrupts Go to: www.freescale.com VALID SCI REQUEST M68HC11E Family — ...

  • Page 107

    ... Freescale Semiconductor, Inc. 5.6 Low-Power Operation Both stop mode and wait mode suspend CPU operation until a reset or interrupt occurs. Wait mode suspends processing and reduces power consumption to an intermediate level. Stop mode turns off all on-chip clocks and reduces power consumption to an absolute minimum while retaining the contents of the entire RAM array ...

  • Page 108

    ... Freescale Semiconductor, Inc. Resets and Interrupts sequence results in which all I/O pins and functions are also restored to their initial states. To use the IRQ pin as a means of recovering from stop, the I bit in the CCR must be clear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from stop regardless of the state of the X bit in the CCR, although the recovery sequence depends on the state of the X bit ...

  • Page 109

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 6.1 Introduction All M68HC11 E-series MCUs have five input/output (I/O) ports and I/O lines, depending on the operating mode. Refer to ports and their shared functions. Port Port A Port B Port C Port D Port E Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at reset ...

  • Page 110

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports Address: Read: Write: Reset: Alternate function: And/or: Address: Read: Write: Reset: Figure 6-2. Pulse Accumulator Control Register (PACTL) DDRA7 — Data Direction for Port A Bit 7 Overridden if an output compare function is configured to control the PA7 pin ...

  • Page 111

    ... Freescale Semiconductor, Inc. 6.3 Port B In single-chip or bootstrap modes, port B pins are general-purpose outputs. In expanded or special test modes, port B pins are high-order address outputs. Address: Single-chip or bootstrap modes: Read: Write: Reset: Expanded or special test modes: Read: Write: Reset: 6.4 Port C In single-chip and bootstrap modes, port C pins reset to high-impedance inputs. ...

  • Page 112

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports Address: Read: Write: Reset: PORTCL is used in the handshake clearing mechanism. When an active edge occurs on the STRA pin, port C data is latched into the PORTCL register. Reads of this register return the last value latched into PORTCL and clear STAF flag (following a read of PIOC with STAF set) ...

  • Page 113

    ... Freescale Semiconductor, Inc. Address: Read: Write: Reset: Bits [7:6] — Unimplemented Always read 0 DDRD[5:0] — Port D Data Direction Bits When DDRD bit and MSTR = 1 in SPCR, PD5/ general-purpose output and mode fault logic is disabled Input 1 = Output 6.6 Port E Port E is used for general-purpose static inputs or pins that share functions with the analog-to-digital (A/D) converter system ...

  • Page 114

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports Full handshake modes use port C pins and the STRA and STRB lines. Input and output handshake modes are supported, and output handshake mode has a 3-stated variation. STRA is an edge-detecting input and STRB is a handshake output ...

  • Page 115

    ... Freescale Semiconductor, Inc. Table 6-2. Parallel I/O Control (Continued) STAF Clearing HNDS Sequence Full- Read output PIOC with hand- STAF = 1 1 shake then write mode PORTCL Address: Read: Write: Reset: STAF — Strobe A Interrupt Status Flag STAF is set when the selected edge occurs on strobe A. This bit can be cleared by a read of PIOC with STAF set followed by a read of PORTCL (simple strobed or full input handshake mode write to PORTCL (output handshake mode) ...

  • Page 116

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports PLS — Pulsed/Interlocked Handshake Operation Bit HNDS must be set to 1 for this bit to have meaning. When interlocked handshake is selected, strobe B is active until the selected edge of strobe A is detected Interlocked handshake 1 = Pulsed handshake (Strobe B pulses high for two E-clock cycles.) EGA — ...

  • Page 117

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 7.1 Introduction The serial communications interface (SCI universal asynchronous receiver transmitter (UART), one of two independent serial input/output (I/O) subsystems in the M68HC11 E series of microcontrollers. It has a standard non-return-to-zero (NRZ) format (one start bit , eight or nine data bits, and one stop bit). Several baud rates are available ...

  • Page 118

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) serial shift register. The output of the serial shift register is applied to TxD as long as transmission is in progress or the transmit enable (TE) bit of serial communication control register 2 (SCCR2) is set. The block diagram, shows the transmit serial shift register and the buffer logic at the top of the figure. ...

  • Page 119

    ... Freescale Semiconductor, Inc. 7.4 Receive Operation During receive operations, the transmit sequence is reversed. The serial shift register receives data and transfers parallel receive data register (SCDR complete word. This double buffered operation allows a character to be shifted in serially while another character is already in the SCDR. An advanced data recovery scheme distinguishes valid data from noise in the serial data stream ...

  • Page 120

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) RECEIVER BAUD RATE CLOCK DDD0 SEE NOTE PIN BUFFER PD0 AND CONTROL RxD DISABLE DRIVER SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Note: Refer to Figure B-1. EVBU Schematic Diagram Figure 7-2. SCI Receiver Block Diagram ...

  • Page 121

    ... Freescale Semiconductor, Inc. 7.5.2 Address-Mark Wakeup The serial characters in this type of wakeup consist of seven (eight information bits and an MSB, which indicates an address character (when set mark). The first character of each message is an addressing character (MSB = 1). All receivers in the system evaluate this character to determine if the remainder of the message is directed toward this particular receiver ...

  • Page 122

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 7.7 SCI Registers Five addressable registers are associated with the SCI: • Four control and status registers: – – – – • One data register: – The SCI registers are the same for all M68HC11 E-series devices with one exception ...

  • Page 123

    ... Freescale Semiconductor, Inc. 7.7.2 Serial Communications Control Register 1 The SCCR1 register provides the control bits that determine word length and select the method used for the wakeup feature. Address: Read: Write: Reset: Figure 7-4. Serial Communications Control Register 1 (SCCR1) R8 — Receive Data Bit bit is set, R8 stores the ninth bit in the receive data character. T8 — ...

  • Page 124

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 7.7.3 Serial Communications Control Register 2 The SCCR2 register provides the control bits that enable or disable individual SCI functions. Address: Read: Write: Reset: Figure 7-5. Serial Communications Control Register 2 (SCCR2) TIE — Transmit Interrupt Enable Bit ...

  • Page 125

    ... Freescale Semiconductor, Inc. 7.7.4 Serial Communication Status Register The SCSR provides inputs to the interrupt logic circuits for generation of the SCI system interrupt. Address: Read: Write: Reset: Figure 7-6. Serial Communications Status Register (SCSR) TDRE — Transmit Data Register Empty Flag This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then writing to SCDR ...

  • Page 126

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) NF — Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR with NF set and then reading SCDR Unanimous decision 1 = Noise detected FE — Framing Error Flag FE is set when detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR ...

  • Page 127

    ... Freescale Semiconductor, Inc. Prescaler Selects SCP2 SCP1 SCP0 SCR2 SCR1 SCR0 Shaded areas reflect standard baud rates. On MC68HC(7)11E20 do not set SCP1 or SCP0 when SCP2 is 1. M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product, Table 7-1. Baud Rate Values Baud 4 ...

  • Page 128

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCR[2:0] — SCI Baud Rate Select Bits Selects receiver and transmitter bit rate based on output from baud rate prescaler stage. Refer to The prescaler bits, SCP[2:0], determine the highest baud rate, and the SCR[2:0] bits select an additional binary submultiple (÷1, ÷2, ÷4, through ÷128) of this highest baud rate ...

  • Page 129

    ... Freescale Semiconductor, Inc. EXTAL XTAL *SCP2 is present only on MC68HC(7)11E20. 7.8 Status Flags and Interrupts The SCI transmitter has two status flags. These status flags can be read by software (polled) to tell when the corresponding condition exists. Alternatively, a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests when the corresponding condition is present ...

  • Page 130

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) these flags is automatic. Functions that are normally performed in response to the status flags also satisfy the conditions of the clearing sequence. TDRE and TC flags are normally set when the transmitter is first enabled (TE set to 1). The TDRE flag indicates there is room in the transmit queue to store another data character in the TDR ...

  • Page 131

    ... Freescale Semiconductor, Inc. BEGIN FLAG RDRF = TDRE = IDLE = VALID SCI REQUEST M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product RIE = TIE = ILIE = 1? N Figure 7-10. Interrupt Source Resolution Within SCI Serial Communications Interface (SCI) Go to: www.freescale.com Serial Communications Interface (SCI) ...

  • Page 132

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Data Sheet 132 For More Information On This Product, Serial Communications Interface (SCI) Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 133

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 8.1 Introduction The serial peripheral interface (SPI), an independent serial communications subsystem, allows the MCU to communicate synchronously with peripheral devices, such as: • Frequency synthesizers • Liquid crystal display (LCD) drivers • Analog-to-digital (A/D) converter subsystems • ...

  • Page 134

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) INTERNAL MCU CLOCK DIVIDER ÷2 ÷4 ÷16 ÷32 SELECT SPI CONTROL SPI STATUS REGISTER SPI INTERRUPT REQUEST 8.3 SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device ...

  • Page 135

    ... Freescale Semiconductor, Inc. SCK CYCLE # SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT MSB (CPHA = 0) DATA OUT SAMPLE INPUT MSB (CPHA = 1) DATA OUT SS (TO SLAVE ASSERTED 2. MASTER WRITES TO SPDR 3. FIRST SCK EDGE 4. SPIF SET 5. SS NEGATED 8.4 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register (SPCR) ...

  • Page 136

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Any SPI output line must have its corresponding data direction bit in DDRD register set. If the DDR bit is clear, that line is disconnected from the SPI logic and becomes a general-purpose input. All SPI input lines are forced to act as inputs regardless of the state of the corresponding DDR bits in DDRD register ...

  • Page 137

    ... Freescale Semiconductor, Inc. between successive SPI characters. In cases where there is only one SPI slave MCU, its SS line can be tied to V 8.6 SPI System Errors Two system errors can be detected by the SPI system. The first type of error arises in a multiple-master system when more than one SPI device simultaneously tries master ...

  • Page 138

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 8.7 SPI Registers The three SPI registers are: • Serial peripheral control register (SPCR) • Serial peripheral status register (SPSR) • Serial peripheral data register (SPDR) These registers provide control, status, and data storage functions. ...

  • Page 139

    ... Freescale Semiconductor, Inc. CPOL — Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device has a steady state low value. When CPOL is set, SCK idles high. Refer to CPHA — Clock Phase Bit The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave ...

  • Page 140

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) WCOL — Write Collision Bit Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access of SPDR. Refer to System write collision 1 = Write collision Bit 5 — Unimplemented Always reads 0 MODF — Mode Fault Bit To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR ...

  • Page 141

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 9.1 Introduction The M68HC11 timing system is composed of five clock divider chains. The main clock divider chain includes a 16-bit free-running counter, which is driven by a programmable prescaler. The main timer’s programmable prescaler provides one of the four clocking rates to drive the 16-bit counter ...

  • Page 142

    ... Freescale Semiconductor, Inc. Timing System OSCILLATOR AND CLOCK GENERATOR (DIVIDE BY FOUR) PRESCALER (÷ 16, 32) SPR[1:0] PRESCALER (÷ 13) SCP[1:0] E ÷ ÷ PRESCALER (÷ 16) PR[1:0] TCNT IC/OC * SCP2 present on MC68HC(7)11E20 only Figure 9-1. Timer Clock Divider Chains Data Sheet 142 For More Information On This Product, PRESCALER ÷ ...

  • Page 143

    ... Freescale Semiconductor, Inc. The COP watchdog clock input (E ÷ 2 chain. The COP automatically times out unless it is serviced within a specific time by a program reset sequence. If the COP is allowed to time out, a reset is generated, which drives the RESET pin low to reset the MCU and the external system ...

  • Page 144

    ... Freescale Semiconductor, Inc. Timing System PRESCALER DIVIDE BY TCNT (HI MCU 16-BIT FREE-RUNNING PR1 PR0 E CLK 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO) 16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH CLK I4/O5 ...

  • Page 145

    ... Freescale Semiconductor, Inc. 9.3 Input Capture The input capture function records the time an external event occurs by latching the value of the free-running counter when a selected edge is detected at the associated timer input pin. Software can store latched values and use them to compute the periodicity and duration of events. For example, by storing the times of successive edges of an incoming signal, software can determine the period and pulse width of a signal ...

  • Page 146

    ... Freescale Semiconductor, Inc. Timing System 9.3.1 Timer Control Register 2 Use the control bits of this register to program input capture functions to detect a particular edge polarity on the corresponding timer input pin. Each of the input capture functions can be independently configured to detect rising edges only, falling edges only, any edge (rising or falling disable the input capture function ...

  • Page 147

    ... Freescale Semiconductor, Inc. Register name: Timer Input Capture 1 Register (High) Read: Write: Reset: Register name: Timer Input Capture 1 Register (Low) Read: Write: Reset: Register name: Timer Input Capture 2 Register (High) Read: Write: Reset: Register name: Timer Input Capture 2 Register (Low) Read: ...

  • Page 148

    ... Freescale Semiconductor, Inc. Timing System 9.3.3 Timer Input Capture 4/Output Compare 5 Register Use TI4/O5 as either an input capture register or an output compare register, depending on the function chosen for the PA3 pin. To enable input capture pin, set the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level 1 ...

  • Page 149

    ... Freescale Semiconductor, Inc. register is compared to the free-running counter value during each E-clock cycle match is found, the particular output compare flag is set in timer interrupt flag register 1 (TFLG1). If that particular interrupt is enabled in the timer interrupt mask register 1 (TMSK1), an interrupt is generated. In addition to an interrupt, a specified action can be initiated at one or more timer output pins ...

  • Page 150

    ... Freescale Semiconductor, Inc. Timing System Register name: Timer Output Compare 2 Register (High) Read: Write: Reset: Register name: Timer Output Compare 2 Register (Low) Read: Write: Reset: Register name: Timer Output Compare 3 Register (High) Read: Write: Reset: Register name: Timer Output Compare 3 Register (Low) ...

  • Page 151

    ... Freescale Semiconductor, Inc. 9.4.2 Timer Compare Force Register The CFORC register allows forced early compares. FOC[1:5] correspond to the five output compares. These bits are set for each output compare that forced. The action taken as a result of a forced compare is the same as if there were a match between the OCx register and the free-running counter, except that the corresponding interrupt status flag bits are not set ...

  • Page 152

    ... Freescale Semiconductor, Inc. Timing System 9.4.3 Output Compare Mask Register Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits of the OC1M register correspond to PA[7:3]. Address: Read: Write: Reset: OC1M[7:3] — Output Compare Masks ...

  • Page 153

    ... Freescale Semiconductor, Inc. next CPU cycle so that a double-byte read returns the full 16-bit state of the counter at the time of the MSB read cycle. Register name: Timer Counter Register (High) Read: Write: Reset: Register name: Timer Counter Register (Low) Read: Write: Reset: 9.4.6 Timer Control Register 1 The bits of this register specify the action taken as a result of a successful OCx compare ...

  • Page 154

    ... Freescale Semiconductor, Inc. Timing System 9.4.7 Timer Interrupt Mask 1 Register Use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts. Address: Read: Write: Reset: OC1I–OC4I — Output Compare x Interrupt Enable Bits If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested. I4/O5I — ...

  • Page 155

    ... Freescale Semiconductor, Inc. 9.4.9 Timer Interrupt Mask 2 Register Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The timer prescaler control bits are included in this register. Address: Read: Write: Reset: TOI — Timer Overflow Interrupt Enable Bit 0 = TOF interrupts disabled 1 = Interrupt requested when TOF is set to 1 RTII — ...

  • Page 156

    ... Freescale Semiconductor, Inc. Timing System 9.4.10 Timer Interrupt Flag Register 2 Bits in this register indicate when certain timer system events have occurred. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position ...

  • Page 157

    ... Freescale Semiconductor, Inc. The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted except by reset. This clock causes the time between successive RTI timeouts constant that is independent of the software latencies associated with flag clearing and service. For this reason, an RTI period starts from the previous timeout, not from when RTIF is cleared ...

  • Page 158

    ... Freescale Semiconductor, Inc. Timing System 9.5.2 Timer Interrupt Flag Register 2 Bits of this register indicate the occurrence of timer system events. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position ...

  • Page 159

    ... Freescale Semiconductor, Inc. 9.5.3 Pulse Accumulator Control Register Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits control the pulse accumulator and IC4/OC5 functions. Address: Read: Write: Reset: DDRA7 — Data Direction for Port A Bit 7 Refer to PAEN — ...

  • Page 160

    ... Freescale Semiconductor, Inc. Timing System 9.7 Pulse Accumulator The M68HC11 Family of MCUs has an 8-bit counter that can be configured to operate either as a simple event counter or for gated time accumulation, depending on the state of the PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, counter is clocked to increasing values by an external pin ...

  • Page 161

    ... Freescale Semiconductor, Inc. Crystal Frequency 4.0 MHz 8.0 MHz 12.0 MHz Pulse accumulator control bits are also located within two timer registers, TMSK2 and TFLG2, as described in the following paragraphs. 9.7.1 Pulse Accumulator Control Register Four of this register’s bits control an 8-bit pulse accumulator system. Another bit enables either the OC5 function or the IC4 function, while two other bits select the rate for the real-time interrupt system ...

  • Page 162

    ... Freescale Semiconductor, Inc. Timing System DDRA3 — Data Direction for Port A Bit 3 Refer to I4/O5 — Input Capture 4/Output Compare 5 Bit 0 = Output compare 5 function enable (no IC4 Input capture 4 function enable (no OC5) RTR[1:0] — RTI Interrupt Rate Select Bits Refer to 9.7.2 Pulse Accumulator Count Register This 8-bit read/write register contains the count of external input events at the PAI input or the accumulated count ...

  • Page 163

    ... Freescale Semiconductor, Inc. PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF to $00. To clear this status bit, write the corresponding data bit position (bit 5) of the TFLG2 register. The PAOVI control bit allows configuring the pulse accumulator overflow for polled or interrupt-driven operation and does not affect the state of PAOVF ...

  • Page 164

    ... Freescale Semiconductor, Inc. Timing System Data Sheet 164 For More Information On This Product, Timing System Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 165

    ... Freescale Semiconductor, Inc. Data Sheet — M68HC11E Family 10.1 Introduction This section contains electrical specifications for the M68HC11 E-series devices. 10.2 Maximum Ratings for Standard and Extended Voltage Devices Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it ...

  • Page 166

    ... Freescale Semiconductor, Inc. Electrical Characteristics 10.3 Functional Operating Range Rating Operating temperature range MC68HC(7)11Ex MC68HC(7)11ExC MC68HC(7)11ExV MC68HC(7)11ExM MC68HC811E2 MC68HC811E2C MC68HC811E2V MC68HC811E2M MC68L11Ex Operating voltage range 10.4 Thermal Characteristics Characteristic Average junction temperature Ambient temperature Package thermal resistance (junction-to-ambient) 48-pin plastic DIP (MC68HC811E2 only) ...

  • Page 167

    ... Freescale Semiconductor, Inc. 10.5 DC Electrical Characteristics Characteristics (2) Output voltage = ±±10.0 µA I Load All outputs except XTAL All outputs except XTAL, RESET, and MODA (2) Output high voltage I = –0.8 mA 4.5 V Load DD All outputs except XTAL, RESET, and MODA Output low voltage I = 1.6 mA ...

  • Page 168

    ... Freescale Semiconductor, Inc. Electrical Characteristics 10.6 Supply Currents and Power Dissipation Characteristics (2) Run maximum total supply current Single-chip mode2 MHz 3 MHz Expanded multiplexed mode2 MHz 3 MHz (2) Wait maximum total supply current (all peripheral functions shut down) Single-chip mode2 MHz 3 MHz Expanded multiplexed mode2 MHz ...

  • Page 169

    ... Freescale Semiconductor, Inc. 10.7 MC68L11E9/E20 DC Electrical Characteristics Characteristics (2) Output voltage = ±±10.0 µA I Load All outputs except XTAL All outputs except XTAL, RESET, and MODA (2) Output high voltage I = –0.5 mA 3.0 V Load –0.8 mA 4.5 V Load DD All outputs except XTAL, RESET, and MODA ...

  • Page 170

    ... Freescale Semiconductor, Inc. Electrical Characteristics 10.8 MC68L11E9/E20 Supply Currents and Power Dissipation Characteristic (2) Run maximum total supply current Single-chip mode Expanded multiplexed mode (2) Wait maximum total supply current (all peripheral functions shut down) Single-chip mode Expanded multiplexed mode ...

  • Page 171

    ... Freescale Semiconductor, Inc CLOCKS, STROBES INPUTS ~ V DD OUTPUTS ~ TESTING ~ V DD CLOCKS, STROBES INPUTS OUTPUTS TESTING Notes: 1. Full test loads are applied during all dc electrical tests and ac timing measurements. 2. During ac timing measurements, inputs are driven to 0.4 volts and V measurements are taken at 20% and 70 M68HC11E Family — ...

  • Page 172

    ... Freescale Semiconductor, Inc. Electrical Characteristics 10.9 Control Timing (1) (2) Characteristic Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup time PCSU CYC Reset input pulse width To guarantee external reset vector Minimum input time (can be pre-empted by internal reset) ...

  • Page 173

    ... Freescale Semiconductor, Inc. 10.10 MC68L11E9/E20 Control Timing Characteristic Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup time PCSU CYC Reset input pulse width To guarantee external reset vector Minimum input time (can be pre-empted by internal reset) Mode programming setup time ...

  • Page 174

    ... Freescale Semiconductor, Inc. Electrical Characteristics Data Sheet 174 For More Information On This Product, Electrical Characteristics Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 175

    ... Freescale Semiconductor, Inc. M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product, Electrical Characteristics Go to: www.freescale.com Electrical Characteristics MC68L11E9/E20 Control Timing Data Sheet 175 ...

  • Page 176

    ... Freescale Semiconductor, Inc. Electrical Characteristics Data Sheet 176 For More Information On This Product, Electrical Characteristics Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 177

    ... Freescale Semiconductor, Inc. M68HC11E Family — Rev. 5 MOTOROLA For More Information On This Product, Electrical Characteristics Go to: www.freescale.com Electrical Characteristics MC68L11E9/E20 Control Timing Data Sheet 177 ...

  • Page 178

    ... Freescale Semiconductor, Inc. Electrical Characteristics 10.11 Peripheral Port Timing (1) (2) Characteristic Frequency of operation E-clock frequency E-clock period Peripheral data setup time MCU read of ports and E Peripheral data hold time MCU read of ports and E Delay time, peripheral data write 100 ns PWD ...

  • Page 179

    ... Freescale Semiconductor, Inc. 10.12 MC68L11E9/E20 Peripheral Port Timing (1) (2) Characteristic Frequency of operation E-clock frequency E-clock period Peripheral data setup time MCU read of ports and E Peripheral data hold time MCU read of ports and E Delay time, peripheral data write 150 ns PWD CYC ...

  • Page 180

    ... Freescale Semiconductor, Inc. Electrical Characteristics Figure 10-8. Port Write Timing Diagram Figure 10-9. Simple Input Strobe Timing Diagram E E PORT B PORT B PREVIOUS PORT DATA PREVIOUS PORT DATA STRB (OUT) STRB (OUT) Figure 10-10. Simple Output Strobe Timing Diagram E E “READY” ...

  • Page 181

    ... Freescale Semiconductor, Inc. WRITE PORTCL WRITE PORTCL E E PREVIOUS PORT DATA PORT C (OUT) PORT C (OUT) PREVIOUS PORT DATA STRB (IN) STRB (OUT) STRA (IN) STRA (IN) NOTES: Notes: 1. After reading PIOC with STAF set 1. After reading PIOC with STAF set 2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1). ...

  • Page 182

    ... Freescale Semiconductor, Inc. Electrical Characteristics 10.13 Analog-to-Digital Converter Characteristics (1) Characteristic Resolution Number of bits resolved by A/D converter Maximum deviation from the ideal A/D transfer Non-linearity characteristics Difference between the output of an ideal and an Zero error actual for 0 input voltage Difference between the output of an ideal and an ...

  • Page 183

    ... Freescale Semiconductor, Inc. 10.14 MC68L11E9/E20 Analog-to-Digital Converter Characteristics (1) Characteristic Resolution Number of bits resolved by A/D converter Maximum deviation from the ideal A/D transfer Non-linearity characteristics Difference between the output of an ideal and an Zero error actual for 0 input voltage Difference between the output of an ideal and an ...

  • Page 184

    ... Freescale Semiconductor, Inc. Electrical Characteristics 10.15 Expansion Bus Timing Characteristics Num Characteristic Frequency of operation (E-clock frequency) 1 Cycle time (2) 2 Pulse width, E low , (2) 3 Pulse width, E high , and AS rise time 4b E and AS fall time (2) (3)a 9 Address hold time , Non-multiplexed address valid time to E rise ...

  • Page 185

    ... Freescale Semiconductor, Inc. 10.16 MC68L11E9/E20 Expansion Bus Timing Characteristics Num Characteristic Frequency of operation (E-clock frequency) 1 Cycle time Pulse width, E low 1 Pulse width, E high 1 and AS rise time 4b E and AS fall time (2) (2)a 9 Address hold time , Non-multiplexed address valid time to E rise ...

  • Page 186

    ... Freescale Semiconductor, Inc. Electrical Characteristics E E R/W, ADDRESS R/W, ADDRESS (NON-MUX) NON-MULTIPLEXED 36 36 READ READ ADDRESS/DATA ADDRESS/DATA (MULTIPLEXED) MULTIPLEXED WRITE WRITE NOTE: Measurement points shown are 20% and 70 Note: Measurement points shown are 20% and 70 Figure 10-14. Multiplexed Expansion Bus Timing Diagram Data Sheet ...

  • Page 187

    ... Freescale Semiconductor, Inc. 10.17 Serial Peripheral Interface Timing Characteristics (1) Num Characteristic Frequency of operation E clock E-clock period Operating frequency Master Slave Cycle time 1 Master Slave (2) Enable lead time 2 Slave (2) Enable lag time 3 Slave Clock (SCK) high time 4 Master Slave Clock (SCK) low time ...

  • Page 188

    ... Freescale Semiconductor, Inc. Electrical Characteristics 10.18 MC68L11E9/E20 Serial Peirpheral Interface Characteristics (1) Num Characteristic Frequency of operation E clock E-clock period Operating frequency Master Slave Cycle time 1 Master Slave (2) Enable lead time 2 Slave (2) Enable lag time 3 Slave Clock (SCK) high time 4 Master Slave Clock (SCK) low time ...

  • Page 189

    ... Freescale Semiconductor, Inc. SS INPUT SCK CPOL = 0 SEE NOTE INPUT SCK CPOL = 1 SEE NOTE OUTPUT 6 MISO INPUT MOSI MASTER MSB OUT OUTPUT Note: This first clock edge is generated internally but is not seen at the SCK pin HELD HIGH ON MASTER. INPUT SCK CPOL = 0 INPUT ...

  • Page 190

    ... Freescale Semiconductor, Inc. Electrical Characteristics SS INPUT SCK CPOL = 0 INPUT 2 SCK CPOL = 1 INPUT 8 MISO SLAVE OUTPUT 6 MOSI MSB IN INPUT Note: Not defined but normally MSB of character just received SS INPUT SCK CPOL = 0 INPUT 2 SCK CPOL = 1 INPUT 8 MISO SEE OUTPUT NOTE MOSI INPUT Note: Not defined but normally LSB of character previously transmitted Figure 11-15 ...

  • Page 191

    ... Freescale Semiconductor, Inc. 10.19 EEPROM Characteristics (1) Characteristic (2) Programming time < 1.0 MHz, RCO enabled 1.0 to 2.0 MHz, RCO disabled ≥ 2.0 MHz (or anytime RCO enabled) (2) Erase time Byte, row, and bulk Write/erase endurance Data retention = 5.0 Vdc ±10 Vdc The RC oscillator (RCO) must be enabled (by setting the CSEL bit in the OPTION register) for EEPROM programming and erasure when the E-clock frequency is below 1 ...

  • Page 192

    ... Freescale Semiconductor, Inc. Electrical Characteristics Data Sheet 192 For More Information On This Product, Electrical Characteristics Go to: www.freescale.com M68HC11E Family — Rev. 5 MOTOROLA ...

  • Page 193

    ... Go to: www.freescale.com Frequency MC Order Number 2 MHz MC68HC11E9BCFN2 3 MHz MC68HC11E9BCFN3 2 MHz MC68HC11E1CFN2 3 MHz MC68HC11E1CFN3 2 MHz MC68HC11E1VFN2 2 MHz MC68HC11E1MFN2 2 MHz MC68HC11E0CFN2 3 MHz MC68HC11E0CFN3 2 MHz MC68HC11E0VFN2 2 MHz MC68HC11E0MFN2 Data Sheet 193 ...

  • Page 194

    ... Freescale Semiconductor, Inc. Ordering Information and Mechanical Specifications Description 52-pin plastic leaded chip carrier (PLCC) (Continued) OTPROM OTPROM, enhanced security feature 20 Kbytes OTPROM No ROM, 2 Kbytes EEPROM 64-pin quad flat pack (QFP) BUFFALO ROM No ROM No ROM, no EEPROM 20 Kbytes OTPROM 52-pin thin quad flat pack (TQFP) ...

  • Page 195

    ... Freescale Semiconductor, Inc. Description 52-pin windowed ceramic leaded chip carrier (CLCC) EPROM 20 Kbytes EPROM 48-pin dual in-line package (DIP) — MC68HC811E2 only No ROM, 2 Kbytes EEPROM 56-pin dual in-line package with 0.70-inch lead spacing (SDIP) BUFFALO ROM No ROM No ROM, no EEPROM M68HC11E Family — Rev. 5 ...

  • Page 196

    ... Freescale Semiconductor, Inc. Ordering Information and Mechanical Specifications 11.3 Custom ROM Device Ordering Information Description 52-pin plastic leaded chip carrier (PLCC) Custom ROM 20 Kbytes custom ROM 64-pin quad flat pack (QFP) Custom ROM 64-pin quad flat pack (continued) 20 Kbytes Custom ROM ...

  • Page 197

    ... Freescale Semiconductor, Inc. 11.4 Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc) Description 52-pin plastic leaded chip carrier (PLCC) Custom ROM No ROM No ROM, no EEPROM 64-pin quad flat pack (QFP) Custom ROM No ROM No ROM, no EEPROM 52-pin thin quad flat pack ( mm) ...

  • Page 198

    ... Freescale Semiconductor, Inc. Ordering Information and Mechanical Specifications 11.5 52-Pin Plastic-Leaded Chip Carrier (Case 778) –N– –L– 0.010 (0.25) T L– VIEW S Data Sheet 198 Ordering Information and Mechanical Specifications For More Information On This Product BRK D Z –M– ...

  • Page 199

    ... Freescale Semiconductor, Inc. 11.6 52-Pin Windowed Ceramic-Leaded Chip Carrier (Case 778B) -A- R 0.51 (0.020 M68HC11E Family — Rev. 5 MOTOROLA Ordering Information and Mechanical Specifications For More Information On This Product, Ordering Information and Mechanical Specifications 52-Pin Windowed Ceramic-Leaded Chip Carrier (Case 778B) ...

  • Page 200

    ... Freescale Semiconductor, Inc. Ordering Information and Mechanical Specifications 11.7 64-Pin Quad Flat Pack (Case 840C DETAIL –D– A 0.20 (0.008 0.05 (0.002) A–B S 0.20 (0.008 DETAIL DETAIL C Data Sheet 200 Ordering Information and Mechanical Specifications For More Information On This Product A–B ...