MC68HC908GR16VFJ Freescale Semiconductor, MC68HC908GR16VFJ Datasheet

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MC68HC908GR16 Data Sheet M68HC08 Microcontrollers MC68HC908GR16 Rev. 5.0 04/2007 freescale.com freescale.com ...

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... Table 4-4. Example Filter Component Values — Table updated to reflect new resistor values Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004, 2007. All rights reserved. ...

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... Figure 14-6. ESCI Receiver Block — Added CGMXCLK OR to BUS CLOCK designator — Replaced description of the LINT and and 17.5 TBM Interrupt MC68HC908GR16 Data Sheet, Rev. 5.0 Page Number(s) — Replaced TMCLKSEL with Rate— Freescale Semiconductor 22 29 and 78 168 172 173 253 255 ...

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... Chapter 15 System Integration Module (SIM 177 Chapter 16 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Chapter 17 Timebase Module (TBM 217 Chapter 18 Timer Interface Module (TIM 221 Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 269 Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 5 ...

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... List of Chapters 6 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.1.2 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.1.3 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.1.4 FLASH Program/Read Operation 2.6.1.5 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.1.6 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Freescale Semiconductor Chapter 1 General Description and and DDA SSA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CGMXFC /V and V ...

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... Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8 Chapter 3 Analog-to-Digital Converter (ADC DDAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SSAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 REFL ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Chapter 4 Clock Generator Module (CGM) MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.4 Power-On Reset 6.3.5 Internal Reset 6.3.6 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.7 COPD (COP Disable Freescale Semiconductor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SSA Chapter 5 Configuration Register (CONFIG) Chapter 6 MC68HC908GR16 Data Sheet, Rev. 5.0 9 ...

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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.2 Features 105 9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.4 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10 Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... Serial Peripheral Interface Module (SPI 114 10.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.12 Timer Interface Module (TIM1 and TIM2 114 10.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Freescale Semiconductor Chapter 10 Low-Power Modes MC68HC908GR16 Data Sheet, Rev. 5.0 11 ...

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... Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.5.2 Data Direction Register 131 12.5.3 Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.6 Port 133 12.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.6.2 Data Direction Register 134 12 Chapter 11 Low-Voltage Inhibit (LVI) Chapter 12 Input/Output Ports (PORTS) MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Freescale Semiconductor Chapter 13 Resets and Interrupts Chapter 14 MC68HC908GR16 Data Sheet, Rev. 5.0 13 ...

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... Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.3.2.6 Monitor Mode Entry Module Reset (MODRST 184 14 Chapter 15 System Integration Module (SIM) MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.12.1 MISO (Master In/Slave Out 210 Freescale Semiconductor Chapter 16 MC68HC908GR16 Data Sheet, Rev. 5.0 15 ...

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... TIM During Break Interrupts 230 18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 18.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 18.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 18.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 16 Chapter 17 Timebase Module (TBM) Chapter 18 Timer Interface Module (TIM) MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 20.9 Clock Generation Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 20.9.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 20.9.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 20.10 5.0-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 20.11 3.3-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Freescale Semiconductor Chapter 19 Development Support Chapter 20 Electrical Specifications MC68HC908GR16 Data Sheet, Rev. 5.0 17 ...

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... Table of Contents 20.12 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 20.13 5.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 20.14 3.3-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 20.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Ordering Information and Mechanical Specifications 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 21.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18 Chapter 21 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... Master reset pin and power-on reset (POR) • 16 Kbytes of on-chip 100k cycle write/erase capable FLASH memory 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor (1) MC68HC908GR16 Data Sheet, Rev. 5.0 19 ...

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... Port bits: PTB0–PTB7; 8-channel ADC module – Port C is only 7 bits: PTC0–PTC6 – Port bits: PTD0–PTD7; shared with SPI, TIM1, and TIM2 modules – Port E is only 6 bits: PTE0–PTE5; shared with ESCI module 20 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908GR16. 1.4 Pin Assignments Figure 1-2 and Figure 1-3 illustrate the pin assignments for the 32-pin LQFP and 48-pin LQFP respectively. Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 MCU Block Diagram 21 ...

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... PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...

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... PTE0/TxD PTE1/RxD PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK Figure 1-2. 32-Pin LQFP Pin Assignments RST PTE0/TxD PTE1/RxD PTE2 PTE3 PTE4 PTE5 IRQ PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK Figure 1-3. 48-Pin LQFP Pin Assignments Freescale Semiconductor RST IRQ MC68HC908GR16 Data Sheet, Rev. 5.0 Pin Assignments ...

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... Chapter 15 System Integration Module (SIM). 1.5.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Chapter 8 External Interrupt (IRQ). 24 and MCU 0.1 μ Figure 1-4. Power Supply Bypassing MC68HC908GR16 Data Sheet, Rev. 5.0 Figure 1 Chapter 4 Freescale Semiconductor ...

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... TIM2) pins. See Peripheral Interface (SPI) Module, and These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. Freescale Semiconductor and V ) DDA SSA ...

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... Any unused inputs and I/O ports should be tied to an appropriate logic level (either require termination, termination is recommended to reduce the possibility of static damage. 26 and Chapter 12 Input/Output Ports NOTE ). Although the I/O ports of the MC68HC908GR16 do not MC68HC908GR16 Data Sheet, Rev. 5.0 Chapter 14 Enhanced Serial (PORTS). Freescale Semiconductor ...

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... BRKH • $FE0A; break address register low, BRKL • $FE0B; break status and control register, BRKSCR • $FE0C; LVI status register, LVISR • $FF7E; FLASH block protect register, FLBPR Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 Figure 2-1, includes: (Figure 2-1) 27 ...

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... INTERRUPT STATUS REGISTER 3 (INT3) RESERVED FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) LVI STATUS REGISTER (LVISR) UNIMPLEMENTED 3 BYTES Figure 2-1. Memory Map MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... Read: Data Direction Register B $0005 (DDRB) Write: See page 126. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor UNIMPLEMENTED 16 BYTES RESERVED FOR COMPATIBILITY WITH MONITOR CODE FOR A-FAMILY PART MONITOR ROM 350 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) ...

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... DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 PSSB3 PSSB2 PSSB1 PSSB0 AFIN ARUN AOVFL ARD8 ARD3 ARD2 ARD1 ARD0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 Reserved U = Unaffected Freescale Semiconductor ...

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... Reset: Read: Timebase Module Control $001C Register (TBCR) Write: See page 220. Reset: Read: IRQ Status and Control $001D Register (INTSCR) Write: See page 103. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Unaffected by reset LOOPS ENSCI ...

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... CH1F 0 CH1IE MS1A Unimplemented R MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 TMBCLK- OSCENIN- ESCIBD- R SEL STOP SRC LVI5OR3 SSREC STOP COPD (Note PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Reserved U = Unaffected Freescale Semiconductor ...

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... Timer 2 Channel 1 Status and $0033 Control Register (T2SC1) Write: See page 234. Reset: Read: Timer 2 Channel 1 $0034 Register High (T2CH1H) Write: See page 236. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Bit Indeterminate after reset Bit ...

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... MC68HC908GR16 Data Sheet, Rev. 5 Bit Bit 0 PRE1 PRE0 VPR1 VPR0 MUL11 MUL10 MUL9 MUL8 MUL3 MUL2 MUL1 MUL0 VRS3 VRS2 VRS1 VRS0 RDS3 RDS2 RDS1 RDS0 ADCH3 ADCH2 ADCH1 ADCH0 AD9 AD9 A3 AD2 AD1 AD0 0 MODE1 MODE0 SBSW (Note Reserved U = Unaffected Freescale Semiconductor ...

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... Reset: Read: Break Status and Control $FE0B Register (BRKSCR) Write: See page 239. Reset: Read: LVI Status Register (LVISR) $FE0C Write: See page 119. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit POR PIN COP ILOP Bit 7 6 ...

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... Figure 2-2. Control, Status, and Data Registers (Sheet Bit BPR7 BPR6 BPR5 BPR4 Unaffected by reset Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 BPR3 BPR2 BPR1 BPR0 = Reserved U = Unaffected Freescale Semiconductor ...

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... Vector Priority Lowest Highest Freescale Semiconductor Table 2-1. Vector Addresses Vector Address $FFDC Timebase Vector (High) IF16 $FFDD Timebase Vector (Low) $FFDE ADC Conversion Complete Vector (High) IF15 $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Vector (High) IF14 $FFE1 Keyboard Vector (Low) ...

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... FLASH control register • $FF7E; FLASH block protect register • $FFDC–$FFFF; these locations are reserved for user-defined interrupt and reset vectors 38 NOTE NOTE NOTE MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. A security feature prevents viewing of the FLASH contents. 2.6.1.1 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: $FE08 Bit 7 Read: 0 Write: ...

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... Any application can use this 4-ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1-ms page erase specification to get a shorter cycle time. 40 NOTE CAUTION MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

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... When in monitor mode, with security sequence failed (see of any FLASH address. 2. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, t Freescale Semiconductor (1) within the FLASH memory address range. NOTE ...

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... This applies particularly to $FFD4–$FFDF. 42 NOTE NOTE PROG maximum defined as the cumulative high voltage HV HV must satisfy this condition 32) <= t maximum HV CAUTION MC68HC908GR16 Data Sheet, Rev. 5.0 maximum, see 20.15 Freescale Semiconductor ...

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... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...

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... With this mechanism, the protect start address can be $XX00, $XX40, $XX80, and $XXC0 (64 bytes page boundaries) within the FLASH memory. 44 NOTE NOTE BPR6 BPR5 BPR4 BPR3 Unaffected by reset. Initial value from factory is 1. MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor TST ...

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... FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode Standby mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. Freescale Semiconductor 16-BIT MEMORY ADDRESS 1 1 ...

Page 46

... Memory 46 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 47

... I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. A read of a port pin in use by the ADC will return a 0. Freescale Semiconductor 3-2. MC68HC908GR16 Data Sheet, Rev. 5.0 ...

Page 48

... PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...

Page 49

... The ADC input voltage must always be greater than DDAD Connect the V DDAD connect the V SSAD The V pin should be routed carefully for maximum noise immunity. DDAD Freescale Semiconductor DDRBx PTBx DISABLE ADC DATA REGISTER ADC VOLTAGE IN (V ADIN ADC ADC CLOCK CLOCK GENERATOR ADIV2– ...

Page 50

... Finally, 8-bit truncation mode will place the eight MSBs in the ADC data register low, ADRL. The two LSBs are dropped. This mode of operation ADC cycles ADC frequency MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 51

... A CPU interrupt is generated if the COCO bit The COCO bit is not used as a conversion complete flag when interrupts are enabled. 3.6 Low-Power Modes The WAIT and STOP instruction can put the MCU in low power-consumption standby modes. Freescale Semiconductor NOTE Figure 3-3. ...

Page 52

... External filtering is often necessary to ensure a clean V DD NOTE carefully and place bypass REFH may improve common mode noise rejection. MC68HC908GR16 Data Sheet, Rev. 5.0 pin to the same voltage DDAD for good results. DDAD pin to the same voltage SSAD REFH REFH close and REFH Freescale Semiconductor for ...

Page 53

... Conversion completed (AIEN = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) The write function of the COCO bit is reserved. When writing to the ADSCR register, always have the COCO bit position. Freescale Semiconductor ) REFL as its lower voltage reference pin. By default, connect the V REFL ...

Page 54

... Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ↓ ↓ ↓ MC68HC908GR16 Data Sheet, Rev. 5.0 Table 3-1. Care should Table 3-1, are used to verify the (1) Input Select PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6 PTB7/AD7 Unused V REFH V REFL ADC power off Freescale Semiconductor ...

Page 55

... ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed. Address: $003D Bit 7 Read: 0 Write: Reset: Address: $003E Read: AD7 Write: Reset: Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL) Freescale Semiconductor AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset = Unimplemented ...

Page 56

... Figure 3-8. ADC Data Register High (ADRH) and Low (ADRL AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset = Unimplemented Unaffected by reset AD8 AD7 AD6 AD5 Unaffected by reset = Unimplemented MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 AD4 AD3 AD2 ADRH 2 1 Bit ADRL AD4 AD3 AD2 Freescale Semiconductor ...

Page 57

... MODE1 and MODE0 select among four modes of operation. The manner in which the ADC conversion results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns right-justified mode 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified signed data mode Freescale Semiconductor ADIV1 ADIV0 ...

Page 58

... Analog-to-Digital Converter (ADC) 58 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 59

... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 4-1 shows the structure of the CGM. Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 59 ...

Page 60

... OSCILLATOR PLL ANALOG AUTOMATIC INTERRUPT MODE CONTROL CONTROL AUTO ACQ PLLIE PRE1–PRE0 FREQUENCY DIVIDER Figure 4-1. CGM Block Diagram MC68HC908GR16 Data Sheet, Rev. 5.0 CGMXCLK (TO: SIM, TIMEBASE, ADC) CLOCK SELECT ÷ 2 CIRCUIT CGMVCLK PLLF Freescale Semiconductor CGMOUT (TO SIM) CGMINT (TO SIM) ...

Page 61

... P and the modulo divider reduces the VCO clock by a factor, N. The dividers’ output is the VCO feedback clock, CGMVDV, running at a frequency, f Programming the PLL for more information.) Freescale Semiconductor , (38.4 kHz) times a linear factor, L, and a power-of-two factor VCLK MC68HC908GR16 Data Sheet, Rev. 5.0 Functional Description ...

Page 62

... Modes. The value of the external capacitor and the 4.5.2 PLL Bandwidth Control 4.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of the Modes.) 4.8 Acquisition/Lock Time Specifications MC68HC908GR16 Data Sheet, Rev. 5.0 Register.) 4.5.2 PLL 4.3.8 Base Clock Selector Circuit.) If Freescale Semiconductor 4.6 for ...

Page 63

... See Specifications. Choose the reference divider After choosing N and P, the actual bus frequency can be determined using equation in 2 above. Freescale Semiconductor 4.8 Acquisition/Lock Time Specifications Register.) , after entering tracking mode before selecting the PLL as the ...

Page 64

... NOM ⎛ ⎞ f VCLK n ⎜ ⎟ -------------------------- L = round ⎝ E ⎠ × NOM MC68HC908GR16 Data Sheet, Rev. 5 integer divisor of f RCLK ⎛ ⎞ ⎫ f VCLKDES ⎜ ⎟ ⎬ ------------------------- - ⎝ f ⎠ ⎭ RCLK ⎞ ⎟ ⎠ and f . VCLK BUS ( Freescale Semiconductor , BUSDES ...

Page 65

... In the PLL reference divider select register (PMDS), program the binary coded equivalent of R. Table 4-1 provides numeric examples (numbers are in hexadecimal notation): f BUS 2.0 MHz 2.4576 MHz 2.5 MHz 4.0 MHz 4.9152 MHz 5.0 MHz 7.3728 MHz 8.0 MHz Freescale Semiconductor E ( × VRS NOM E × f ...

Page 66

... Routing should be done with great care to minimize signal cross talk and noise. See 20.9 Clock Generation Module Characteristics 66 4.3.6 Programming the PLL Circuit. for capacitor and resistor values. MC68HC908GR16 Data Sheet, Rev. 5.0 does not account for three possible Figure Freescale Semiconductor 4-2. ...

Page 67

... The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network. Freescale Semiconductor CGMXCLK CGMXFC OSC2 R F1 ...

Page 68

... CGMINT is the interrupt signal generated by the PLL lock detector DDA NOTE ) SSA NOTE Figure 4-2 shows only the logical relation of CGMXCLK to OSC1 MC68HC908GR16 Data Sheet, Rev. 5.0 pin to the same voltage DDA pin to the same voltage SSA ) and comes XCLK Freescale Semiconductor ...

Page 69

... When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Freescale Semiconductor 4.5.1 PLL Control Register. 4.5.2 PLL Bandwidth Control 4.5.3 PLL Multiplier Select Register 4 ...

Page 70

... VCO clock as the source of the base clock PLLF PLLON BCS PRE1 Figure 4-4. PLL Control Register (PCTL) NOTE NOTE MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 PRE0 VPR1 VPR0 4.3.8 Base Clock Selector 4.3.8 Base Clock Freescale Semiconductor ...

Page 71

... Register.) controls the hardware center-of-range frequency, f the PLLON bit is set. Reset clears these bits. Table 4-3. VPR1 and VPR0 Programming VPR1 and VPR0 not program value of 3. Freescale Semiconductor Circuit.) PLL.) PRE1 and PRE0 cannot be written when the NOTE 4.3.6 Programming the ...

Page 72

... In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode Tracking mode 0 = Acquisition mode LOCK 0 0 ACQ Reserved MC68HC908GR16 Data Sheet, Rev. 5 Bit Freescale Semiconductor ...

Page 73

... PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to $40 for a default multiply value of 64. The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). Freescale Semiconductor ...

Page 74

... VRS7–VRS0 cannot be written when the PLLON bit in the VRS Exceptions.) A value of $00 in the VCO range select Exceptions.) Reset initializes the register to $40 NOTE NOTE RDS3 MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 VRS2 VRS1 VRS0 Register), controls the 4.3.8 Base 2 1 Bit 0 RDS2 RDS1 RDS0 Freescale Semiconductor ...

Page 75

... WAIT exit. This would be the case also when the PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. Freescale Semiconductor 4.3.6 Programming the PLL.) RDS7–RDS0 cannot be written when the 4 ...

Page 76

... Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. 76 Chapter 15 System Integration Module MC68HC908GR16 Data Sheet, Rev. 5.0 (SIM).) Freescale Semiconductor ...

Page 77

... Figure 4-10 F reference frequencies. For reference frequencies between the values listed in the table, extrapolate to the nearest common capacitor value. In general, a slightly larger capacitor provides more stability at the expense of increased lock time. Freescale Semiconductor 4.3.3 PLL Circuits, Register.) 4.8.3 Choosing a . The power supply potential alters the ...

Page 78

... CGMXFC Figure 4-10. PLL Filter 0.15 μ 0.12 μ 0.10 μ MC68HC908GR16 Data Sheet, Rev. 5 SSA ( 0.22 μF 0.18 μF 0.18 μF 0.12 μF 0.12 μF 0.1 μF 0.1 μ Freescale Semiconductor ...

Page 79

... POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Freescale Semiconductor NOTE Figure 5-1 and MC68HC908GR16 Data Sheet, Rev. 5.0 Figure 5-2 ...

Page 80

... This function is used to keep the timebase running while Chapter 17 Timebase Module Module. MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 TMBCLK- OSCEN- ESCIBD- SEL INSTOP SRC Bit 0 SSREC STOP COPD (TBM). When clear, oscillator will cease Chapter 14 Enhanced Serial Chapter 6 Computer Operating Freescale Semiconductor for ...

Page 81

... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled Freescale Semiconductor Chapter 11 Low-Voltage Inhibit Chapter 11 Low-Voltage Inhibit NOTE NOTE Chapter 6 Computer Operating Properly (COP) MC68HC908GR16 Data Sheet, Rev. 5.0 Functional Description (LVI) ...

Page 82

... Configuration Register (CONFIG) 82 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 83

... COPCTL WRITE COPEN (FROM SIM) COP DISABLE (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (FROM CONFIG) Freescale Semiconductor 12-BIT COP PRESCALER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 6-1. COP Block Diagram MC68HC908GR16 Data Sheet, Rev. 5.0 ...

Page 84

... Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 84 NOTE NOTE Figure 6-1. MC68HC908GR16 Data Sheet, Rev. 5.0 . During the break state, TST 6.4 COP Freescale Semiconductor ...

Page 85

... The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. 6.7.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. Freescale Semiconductor ...

Page 86

... STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when present on the RST pin. TST MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 87

... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 87 ...

Page 88

... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H:X) MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 Bit Freescale Semiconductor ...

Page 89

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...

Page 90

... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908GR16 Data Sheet, Rev. 5 Bit Freescale Semiconductor ...

Page 91

... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 Arithmetic/Logic Unit (ALU) ...

Page 92

... REL 27 rr – – – – – – REL – – – – – – REL 28 rr – – – – – – REL 29 rr – – – – – – REL 22 rr Freescale Semiconductor ...

Page 93

... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← ...

Page 94

... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...

Page 95

... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...

Page 96

... DIR 35 dd – – 0 – – – INH 8E DIR BF dd EXT IX2 – – – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...

Page 97

... M Memory location N Negative bit 7.8 Opcode Map See Table 7-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...

Page 98

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

Page 99

... The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only (MODE = 0), the interrupt remains set until a vector fetch, software clear, or reset occurs. Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 99 ...

Page 100

... PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...

Page 101

... The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. Addr. Register Name Read: IRQ Status and Control $001D Register (INTSCR) Write: See page 103. Reset: Freescale Semiconductor V DD CLR IMASK MODE Figure 8-2. IRQ Module Block Diagram NOTE ...

Page 102

... To protect CPU interrupt flags during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags. 102 NOTE Support. MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 103

... IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only Freescale Semiconductor IRQF ...

Page 104

... External Interrupt (IRQ) 104 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 105

... If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled. Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 105 ...

Page 106

... PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...

Page 107

... If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. • Return of all enabled keyboard interrupt pins to 1 — As long as any enabled keyboard interrupt pin the keyboard interrupt remains set. Freescale Semiconductor ACKK V DD CLR ...

Page 108

... The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes. 9.5.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 108 NOTE MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 109

... Bits 7–4 — Not used These read-only bits always read as 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit Keyboard interrupt pending keyboard interrupt pending Freescale Semiconductor 9.7.1 Keyboard Status and Control ...

Page 110

... Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin 110 KBIE6 KBIE5 KBIE4 KBIE3 MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...

Page 111

... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 Chapter 5 ...

Page 112

... CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop is shut off, but the oscillator will continue to operate in stop mode. 112 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 113

... Wait Mode If enabled, the low-voltage inhibit (LVI) module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. Freescale Semiconductor Computer Operating Properly Module (COP) MC68HC908GR16 Data Sheet, Rev. 5.0 ...

Page 114

... The timer interface modules (TIM) remain active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 114 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 115

... Timer 1 interface (TIM1) module interrupt — A CPU interrupt request from the TIM1 loads the program counter with the contents of: – $FFF2 and $FFF3; TIM1 overflow – $FFF4 and $FFF5; TIM1 channel 1 – $FFF6 and $FFF7; TIM1 channel 0 Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 Timebase Module (TBM) voltage resets TRIPF 115 ...

Page 116

... Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal. 116 NOTE MC68HC908GR16 Data Sheet, Rev. 5.0 voltage resets the TRIPF Freescale Semiconductor ...

Page 117

... V TRIPR 0 V which will re-trigger the power-on reset and reset the trip point to 3-V operation. Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI ...

Page 118

... LVI resets allows the LVI TRIPF falls below the V level. In the configuration register, the DD TRIPF MC68HC908GR16 Data Sheet, Rev. 5.0 , which causes the MCU to exit TRIPR LVISTOP FROM CONFIG1 LVI RESET level, software can monitor V DD Freescale Semiconductor Figure Bit polling ...

Page 119

... V 11.5 LVI Interrupts The LVI module does not generate interrupt requests. 11.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. Freescale Semiconductor fall below V ), the LVI will maintain a reset condition until DD TRIPF . This prevents a condition in which the MCU is ...

Page 120

... MCU out of wait mode. 11.6.2 Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 120 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 121

... See page 128. Reset: Read: Port D Data Register $0003 (PTD) Write: See page 130. Reset: Read: Data Direction Register A $0004 (DDRA) Write: See page 124. Reset: Freescale Semiconductor NOTE Bit PTA7 PTA6 PTA5 PTB7 PTB6 PTB5 0 PTC6 PTC5 PTD7 PTD6 PTD5 ...

Page 122

... PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 Unimplemented MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Freescale Semiconductor ...

Page 123

... DDRD3 D 4 DDRD4 5 DDRD5 6 DDRD6 7 DDRD7 0 DDRE0 1 DDRE1 2 DDRE2 E 3 DDRE3 4 DDRE4 5 DDRE5 Freescale Semiconductor DDR Module Control KBIE0 KBIE1 KBIE2 KBIE3 KBD KBIE4 KBIE5 KBIE6 KBIE7 ADC ADCH4–ADCH0 SPI SPE ELS0B:ELS0A TIM1 ELS1B:ELS1A ELS0B:ELS0A TIM2 ELS1B:ELS1A SCI ENSCI MC68HC908GR16 Data Sheet, Rev. 5.0 ...

Page 124

... PTA3 Unaffected by reset KBD6 KBD5 KBD4 KBD3 Figure 12-2. Port A Data Register (PTA) Chapter 9 Keyboard Interrupt Module (KBI DDRA6 DDRA5 DDRA4 DDRA3 NOTE MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 PTA2 PTA1 PTA0 KBD2 KBD1 KBD0 2 1 Bit 0 DDRA2 DDRA1 DDRA0 Freescale Semiconductor ...

Page 125

... Figure 12-5. Port A Input Pullup Enable Register (PTAPUE) PTAPUE7–PTAPUE0 — Port A Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected Freescale Semiconductor DDRAx RESET PTAx V ...

Page 126

... Figure 12-7. Data Direction Register B (DDRB) 126 PTB6 PTB5 PTB4 PTB3 Unaffected by reset AD6 AD5 AD4 AD3 Figure 12-6. Port B Data Register (PTB) NOTE DDRB6 DDRB5 DDRB4 DDRB3 MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 PTB2 PTB1 PTB0 AD2 AD1 AD0 2 1 Bit 0 DDRB2 DDRB1 DDRB0 Freescale Semiconductor ...

Page 127

... X Input, Hi Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. Freescale Semiconductor NOTE DDRBx RESET PTBx Figure 12-8. Port B I/O Circuit Table 12-3 summarizes the operation of the port B pins. Table 12-3. Port B Pin Functions ...

Page 128

... Figure 12-11 shows the port C I/O logic. 128 PTC6 PTC5 PTC4 PTC3 Unaffected by reset R Figure 12-9. Port C Data Register (PTC DDRC6 DDRC5 DDRC4 DDRC3 NOTE MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 PTC2 PTC1 PTC0 = Reserved 2 1 Bit 0 DDRC2 DDRC1 DDRC0 Freescale Semiconductor ...

Page 129

... DDRC is configured for output mode. Address: $000E Bit 7 Read: 0 PTCPUE6 Write: Reset Unimplemented Figure 12-12. Port C Input Pullup Enable Register (PTCPUE) Freescale Semiconductor DDRCx RESET PTCx V DD INTERNAL PULLUP DEVICE Figure 12-11. Port C I/O Circuit Table 12-4 summarizes the operation of the port C pins. ...

Page 130

... SPE, is clear, the SPI module is disabled, and the PTD0/SS pin is available for general-purpose I/O. 130 PTD6 PTD5 PTD4 PTD3 Unaffected by reset T2CH0 T1CH1 T1CH0 SPSCK Chapter 18 Timer Interface Module Chapter 18 Timer Interface Module MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 PTD2 PTD1 PTD0 MOSI MISO SS (TIM). (TIM). Freescale Semiconductor ...

Page 131

... Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from Figure 12-15 shows the port D I/O logic. READ DDRD ($0007) WRITE DDRD ($0007) WRITE PTD ($0003) PTDPUEx READ PTD ($0003) Freescale Semiconductor Table 12- DDRD6 DDRD5 ...

Page 132

... Input, V DDRD7–DDRD0 DD (4) DDRD7–DDRD0 Input, Hi-Z Output DDRD7–DDRD0 PTDPUE5 PTDPUE4 PTDPUE3 MC68HC908GR16 Data Sheet, Rev. 5.0 Accesses to PTD Read Write Pin PTD7–PTD0 Pin PTD7–PTD0 PTD7–PTD0 PTD7–PTD0 2 1 Bit 0 PTDPUE2 PTDPUE1 PTDPUE0 Freescale Semiconductor (3) (3) ...

Page 133

... TxD — SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the ESCI module. When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See Chapter 14 Enhanced Serial Communications Interface (ESCI) Freescale Semiconductor ...

Page 134

... Table 12-6 summarizes the operation of the port E pins. Table 12-6. Port E Pin Functions Accesses to DDRE Read/Write (2) DDRE5–DDRE0 DDRE5–DDRE0 MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 DDRE2 DDRE1 DDRE0 PTEx Accesses to PTE Read Write Pin PTE5–PTE0 PTE5–PTE0 PTE5–PTE0 Freescale Semiconductor (3) ...

Page 135

... A power-on reset (POR internal reset caused by a positive transition on the V POR must go below V to reset the MCU. This distinguishes between a reset and a POR. The POR is POR not a brown-out detector, low-voltage detector, or glitch detector. Freescale Semiconductor , generates an external reset. An external reset sets the PIN bit RL MC68HC908GR16 Data Sheet, Rev. 5.0 pin. V ...

Page 136

... Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay • Sets the LVI bit in the SIM reset status register 136 4096 32 CYCLES CYCLES Figure 13-1. Power-On Reset Recovery is below the LVI DD MC68HC908GR16 Data Sheet, Rev. 5.0 voltage TRIPR voltage and during the oscillator TRIPR Freescale Semiconductor ...

Page 137

... Last reset caused by timeout of COP counter 0 = POR or read of SRSR since any reset ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR since any reset Freescale Semiconductor at that time, then the PIN bit in the SRSR may be set IH NOTE 6 ...

Page 138

... CONDITION CODE REGISTER 1 ACCUMULATOR 2 (1) INDEX REGISTER (LOW BYTE) 3 PROGRAM COUNTER (HIGH BYTE) 4 PROGRAM COUNTER (LOW BYTE) 5 • • • $00FF DEFAULT ADDRESS ON RESET Figure 13-3. Interrupt Stacking Order MC68HC908GR16 Data Sheet, Rev. 5.0 UNSTACKING ORDER Freescale Semiconductor ...

Page 139

... H register or uses the indexed addressing mode, save the H register and then restore it prior to exiting the routine. See Figure 13-5 for a flowchart depicting interrupt processing. 13.3.2 Sources The sources in Table 13-1 can generate CPU interrupt requests. Freescale Semiconductor CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH ...

Page 140

... INSTRUCTION INSTRUCTION 140 YES BREAK ? NO NO YES IRQ ? NO YES CGM ? NO OTHER YES ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR SWI YES ? NO RTI YES UNSTACK CPU REGISTERS ? NO EXECUTE INSTRUCTION Figure 13-5. Interrupt Processing MC68HC908GR16 Data Sheet, Rev. 5.0 SET I BIT Freescale Semiconductor ...

Page 141

... SCI transmitter empty SCI transmission complete Keyboard pin ADC conversion complete Timebase 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction highest priority Freescale Semiconductor Table 13-1. Interrupt Sources INT Register (1) Flag Mask Flag ...

Page 142

... SPI receiver full bit (SPRF) — The SPRF bit is set every time a byte transfers from the shift register to the receive data register. The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU interrupt requests. SPRF is in the SPI status and control register and SPRIE is in the SPI control register. 142 NOTE MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 143

... Parity error bit (PE) — set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, enables PE to generate SCI error CPU interrupt requests SCI status register 1. PEIE is in SCI control register 3. Freescale Semiconductor MC68HC908GR16 Data Sheet, Rev. 5.0 Interrupts ...

Page 144

... Table 13-2. Interrupt Source Flags Interrupt Interrupt Status Source Register Flag MC68HC908GR16 Data Sheet, Rev. 5.0 Table 13-2 summarizes the — — IF1 IF2 IF3 IF4 IF5 IF6 IF7 IF8 IF9 IF10 IF11 IF12 IF13 IF14 IF15 IF16 Freescale Semiconductor ...

Page 145

... R Figure 13-8. Interrupt Status Register 3 (INT3) IF16–IF15 — Interrupt Flags 20–15 This flag indicates the presence of an interrupt request from the source shown Interrupt request present interrupt request present Bits 7–2 — Always read 0 Freescale Semiconductor IF5 IF4 IF3 ...

Page 146

... Resets and Interrupts 146 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 147

... ESCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an ESCI input or output reflects the name of the shared port pin. ESCI I/O pins. The generic pin names appear in the text of this section. Freescale Semiconductor Table 14-1 shows the full names and the generic names of the MC68HC908GR16 Data Sheet, Rev ...

Page 148

... PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 PTD7/T2CH1 PTD6/T2CH0 PTD5/T1CH1 PTD4/T1CH0 PTD3/SPSCK PTD2/MOSI PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE TxD PTE0/TxD Freescale Semiconductor (1) (1) (1) (1) (1) (1) (1) ...

Page 149

... ILIE TE SCTE RE RWU SCRF SBK IDLE WAKEUP CONTROL BUS CLOCK CGMXCLK ÷ 4 SCALER SL SL=1 -> SCI_CLK = BUSCLK SL=0 -> SCI_CLK = CGMXCLK Figure 14-2. ESCI Module Block Diagram Freescale Semiconductor INTERNAL BUS LOOPS RECEIVE FLAG CONTROL CONTROL BKF ENSCI RPF PRE- BAUD RATE GENERATOR DATA SELECTION ÷ ...

Page 150

... SCP0 Unimplemented R MC68HC908GR16 Data Sheet, Rev. 5.0 Figure 14- Bit 0 PSSB3 PSSB2 PSSB1 PSSB0 AFIN ARUN AROVFL ARD8 ARD3 ARD2 ARD1 ARD0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 Reserved Figure 14-4. Freescale Semiconductor ...

Page 151

... SCP1 SCP0 SCR1 SCR2 SCR0 PEN PDS2 PTY PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0 Freescale Semiconductor PARITY 8-BIT DATA FORMAT OR DATA (BIT M IN SCC1 CLEAR) BIT BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 9-BIT DATA FORMAT (BIT M IN SCC1 SET) BIT 2 ...

Page 152

... Receiving a break character has these effects on ESCI registers: • Sets the framing error bit (FE) in SCS1 • Sets the ESCI receiver full bit (SCRF) in SCS1 • Clears the ESCI data register (SCDR) 152 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 153

... Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. Freescale Semiconductor NOTE 1. MC68HC908GR16 Data Sheet, Rev. 5.0 ...

Page 154

... DIVIDER DATA H RECOVERY ALL ZEROS WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE OR ORIE NF NEIE FE FEIE PE PEIE MC68HC908GR16 Data Sheet, Rev. 5.0 ESCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER RWU SCRF IDLE R8 ILIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor Figure ...

Page 155

... When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. 14-2 summarizes the results of the start bit verification samples. Freescale Semiconductor START BIT START BIT START BIT ...

Page 156

... Table 14-2. Start Bit Verification Start Bit Verification Yes Yes Yes No Yes Table 14-3. Data Bit Recovery Data Bit Determination NOTE Table 14-4. Stop Bit Recovery Framing Error Flag MC68HC908GR16 Data Sheet, Rev. 5.0 Noise Flag Noise Flag Table 14-4 Noise Flag Freescale Semiconductor ...

Page 157

... With the misaligned character shown in the count of the transmitting device is 10 bit times × cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: Freescale Semiconductor MSB DATA SAMPLES Figure 14-8 ...

Page 158

... RT cycles at the point when 154 160 – × 100 = 3.90%. ------------------------- - 154 Figure 14-9, the receiver counts 170 RT cycles at the point when 170 176 – × 100 = 3.53%. ------------------------- - 170 MC68HC908GR16 Data Sheet, Rev. 5.0 IDLE OR NEXT CHARACTER Freescale Semiconductor ...

Page 159

... The ESCI module remains active in wait mode. Any enabled CPU interrupt request from the ESCI module can bring the MCU out of wait mode. If ESCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. Freescale Semiconductor NOTE MC68HC908GR16 Data Sheet, Rev. 5.0 Low-Power Modes ...

Page 160

... ESCI control register 1, SCC1 • ESCI control register 2, SCC2 • ESCI control register 3, SCC3 • ESCI status register 1, SCS1 • ESCI status register 2, SCS2 • ESCI data register, SCDR • ESCI baud rate register, SCBR 160 (BRK). MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 161

... M — Mode (Character Length) Bit This read/write bit determines whether ESCI characters are eight or nine bits long (See 14-5).The ninth bit can serve as a receiver wakeup signal parity bit. Reset clears the M bit 9-bit ESCI characters 0 = 8-bit ESCI characters Freescale Semiconductor ...

Page 162

... Odd 1 8 Even 1 8 Odd Table Table 14-3). Reset clears the PEN bit. NOTE MC68HC908GR16 Data Sheet, Rev. 5.0 Character Length 1 10 bits 1 11 bits 1 10 bits 1 10 bits 1 11 bits 1 11 bits 14-5). When enabled, the parity function Freescale Semiconductor ...

Page 163

... Reset clears the TE bit Transmitter enabled 0 = Transmitter disabled Writing to the TE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1. Freescale Semiconductor TCIE ...

Page 164

... When the ESCI is receiving 9-bit characters the read-only ninth bit (bit 8) of the received character received at the same time that the SCDR receives the other 8 bits. 164 NOTE NOTE ORIE Unimplemented R = Reserved MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 NEIE FEIE PEIE Unaffected Freescale Semiconductor ...

Page 165

... Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: $0016 Bit 7 Read: SCTE Write: Reset: 1 Figure 14-13. ESCI Status Register 1 (SCS1) Freescale Semiconductor SCRF IDLE Unimplemented MC68HC908GR16 Data Sheet, Rev. 5.0 I/O Registers 2 1 Bit 0 ...

Page 166

... The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. 166 MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 167

... PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit Parity error detected parity error detected Freescale Semiconductor NORMAL FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 ...

Page 168

... Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register. Do not use read-modify-write instructions on the ESCI data register. 168 Unimplemented Unaffected by reset NOTE MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 0 BKF RPF Bit Freescale Semiconductor ...

Page 169

... The break symbol length must be verified in software in any case, but the LINR bit serves as a filter, preventing false detections of break characters that are really 0x00 data characters. LINT LINR Freescale Semiconductor NOTE LINR SCP1 SCP0 Unimplemented R = Reserved Table 14-6. ESCI LIN Control Bits ...

Page 170

... Table 14-7. ESCI Baud Rate Prescaling Baud Rate Register Prescaler Divisor (BPD Table 14-8. ESCI Baud Rate Selection Baud Rate Divisor (BD 128 NOTE PDS1 PDS0 PSSB4 PSSB3 MC68HC908GR16 Data Sheet, Rev. 5.0 Table 14-7. Reset Table 14-8. Reset clears 2 1 Bit 0 PSSB2 PSSB1 PSSB0 Freescale Semiconductor ...

Page 171

... BPD = Baud rate register prescaler divisor BD = Baud rate divisor PD = Prescaler divisor PDFA = Prescaler divisor fine adjust Table 14-11 shows the ESCI baud rates that can be generated with a 4.9152-MHz bus frequency. Freescale Semiconductor NOTE Table 14-9. ESCI Prescaler Division Ratio Prescaler Divisor (PD Bypass this prescaler ...

Page 172

... MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 173

... Table 14-11. ESCI Baud Rate Selection Examples PS[2:1:0] PSSB[4:3:2:1: Freescale Semiconductor Prescaler SCP[1:0] Divisor SCR[2:1:0] (BPD MC68HC908GR16 Data Sheet, Rev. 5.0 I/O Registers Baud Rate Baud Rate Divisor (f = 4.9152 MHz) Bus (BD) 1 76,800 1 9600 1 9562.65 1 9525.58 1 8563.07 2 38,400 4 19,200 8 9600 16 4800 ...

Page 174

... Bit time measurement has finished 0 = Bit time measurement not yet finished 174 ALOST AFIN AM0 ACLK Unimplemented ESCI Arbiter Mode Idle / counter reset Bit time measurement Bus arbitration Reserved / do not use NOTE MC68HC908GR16 Data Sheet, Rev. 5 Bit 0 ARUN AROVFL ARD8 Freescale Semiconductor ...

Page 175

... The counter is started when detected on RxD (see enabling the bit time measurement with ACLK = 1 leads to immediate start of the counter (see Figure 14-23). The counter will be stopped on the next rising edge of RxD. This mode is used to measure the length of a received break. Freescale Semiconductor ...

Page 176

... If SCI_TxD is sensed 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration operation will be restarted after the next rising edge of SCI_TxD. 176 MEASURED TIME MEASURED TIME MEASURED TIME MC68HC908GR16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...

Page 177

... CGMOUT divided by two) IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal Freescale Semiconductor Table 15-1. Signal Name Conventions Description MC68HC908GR16 Data Sheet, Rev. 5.0 177 ...

Page 178

... PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...

Page 179

... CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. Freescale Semiconductor STOP/WAIT CONTROL ...

Page 180

... R (1) Note ILOP ILAD MODRST LVI IF3 IF2 IF1 IF11 IF10 IF9 IF8 IF19 IF18 IF17 IF16 Reserved TO TBM,TIM1,TIM2, ADC SIM SIMOSCEN SIM COUNTER BUS CLOCK ÷ 2 GENERATORS Freescale Semiconductor Bit IF7 R 0 IF15 R 0 IT12 TO REST OF CHIP IT23 TO REST OF CHIP ...

Page 181

... Figure 15-5 Reset Type POR/LVI All others CGMOUT RST IAB PC Freescale Semiconductor 15.6.2 Stop Mode. 15.4 SIM Counter), but an external reset does not. Each of shows the relative timing. Table 15-2. PIN Bit Set Timing Number of Cycles Required to Set PIN 4163 (4096 + ...

Page 182

... NOTE RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 15-6. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET LVI POR MODRST Figure 15-7. Sources of Internal Reset MC68HC908GR16 Data Sheet, Rev. 5.0 Figure 15-6. VECTOR HIGH Freescale Semiconductor ...

Page 183

... LVI voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin TRIPF (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Freescale Semiconductor 32 CYCLES Figure 15-8. POR Recovery on the RST pin disables the COP module. ...

Page 184

... Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts 184 15.6.2 Stop Mode 15.3.2 Active Resets from Internal Sources MC68HC908GR16 Data Sheet, Rev. 5.0 19.3.1.1 Normal Monitor Mode). for details. The SIM counter is for counter control and Freescale Semiconductor ...

Page 185

... I bit is cleared). See MODULE INTERRUPT I BIT IAB DUMMY SP IDB DUMMY PC – 1[7:0] PC – 1[15:8] R/W MODULE INTERRUPT I BIT IAB SP – 4 IDB CCR R/W Freescale Semiconductor shows interrupt recovery timing. Figure 15-11. SP – – – – Figure 15-9 Interrupt Entry Timing SP – – – – ...

Page 186

... YES INTERRUPT BIT SET? NO IRQ YES INTERRUPT? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION? NO EXECUTE INSTRUCTION Figure 15-11. Interrupt Processing MC68HC908GR16 Data Sheet, Rev. 5.0 SET I BIT Freescale Semiconductor ...

Page 187

... PC – hardware interrupt does. 15.5.1.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Freescale Semiconductor CLI LDA #$FF PSHH ...

Page 188

... SPI receiver full SPI transmitter empty SCI receive error SCI receive SCI transmit Keyboard Timebase module Reserved MC68HC908GR16 Data Sheet, Rev. 5.0 Interrupt Status Register Flag — — I10 I11 I12 I13 I14 I15 I16 2 1 Bit Table 15-3. Freescale Semiconductor ...

Page 189

... SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Freescale Semiconductor ...

Page 190

... WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 15-16. Wait Mode Entry Timing show the timing for WAIT recovery. $6E0B $6E0C $00FF $A6 $A6 $01 $0B MC68HC908GR16 Data Sheet, Rev. 5.0 Figure 15-16 SAME SAME SAME $00FE $00FD $00FC $6E Freescale Semiconductor shows ...

Page 191

... To minimize stop current, all pins configured as inputs should be driven CPUSTOP IAB STOP ADDR IDB R/W Note: Previous data can be operand data or the STOP opcode, depending on the last instruction. Freescale Semiconductor 32 32 CYCLES CYCLES $A6 NOTE Figure 15-19 NOTE STOP ADDR + 1 ...

Page 192

... STOP RECOVERY PERIOD STOP + 2 STOP + 2 Table 15-4 shows the mapping of these registers. Table 15-4. SIM Registers Register BSR SRSR BFCR Reserved MC68HC908GR16 Data Sheet, Rev. 5 – – – 3 Access Mode User User User 2 1 Bit 0 SBSW R R (1) Note Freescale Semiconductor ...

Page 193

... MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR Freescale Semiconductor PIN COP ILOP ...

Page 194

... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break 194 MC68HC908GR16 Data Sheet, Rev. 5 Bit Freescale Semiconductor ...

Page 195

... CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. The full names of the SPI I/O pins are shown in follows. Freescale Semiconductor Table 16-1. The generic pin names appear in the text that MC68HC908GR16 Data Sheet, Rev. 5.0 ...

Page 196

... PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE SPSCK CGND V PTD3/SPSCK SS Freescale Semiconductor (1) ...

Page 197

... See The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 16.13.2 SPI Status and Control master also controls the shift register of the slave peripheral. Freescale Semiconductor Figure 16-3 Register. Bit 7 6 ...

Page 198

... SPTE OVRF MODF Figure 16-3. SPI Module Block Diagram MISO MOSI SPSCK MC68HC908GR16 Data Sheet, Rev. 5.0 0 PIN CONTROL LOGIC M CLOCK LOGIC S CPHA CPOL SPWOM ERRIE SPTIE SPRIE SPE SLAVE MCU MISO MOSI SHIFT REGISTER SPSCK SS Freescale Semiconductor MISO MOSI SPSCK SS ...

Page 199

... Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. Freescale Semiconductor 16.5 Transmission NOTE MC68HC908GR16 Data Sheet, Rev ...

Page 200

... SS; TO SLAVE CAPTURE STROBE Figure 16-5. Transmission Format (CPHA = 0) 200 NOTE 16.7.2 Mode Fault MSB BIT 6 BIT 5 BIT 4 BIT 3 MSB BIT 6 BIT 5 BIT 4 BIT 3 MC68HC908GR16 Data Sheet, Rev. 5.0 Error.) When CPHA = 0, the first BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB Freescale Semiconductor ...