MC68HC908GR16VFJ Freescale Semiconductor, MC68HC908GR16VFJ Datasheet - Page 197

• Manufacturer Part Number: MC68HC908GR16VFJ
• Description: IC MCU 16K FLASH 8MHZ SPI 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR16VFJ

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.4 Functional Description
Figure 16-2
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt
driven.
If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. See
12.4.3 Port C Input Pullup Enable
The following paragraphs describe the operation of the SPI module.
16.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. See
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See
master also controls the shift register of the slave peripheral.
Freescale Semiconductor
Addr.
$0010
$0011
$0012
16.13.2 SPI Status and Control
SPI Status and Control
Register Name
summarizes the SPI I/O registers and
SPI Control Register
Register (SPSCR)
SPI Data Register
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. See
See page 212.
See page 213.
See page 215.
(SPCR)
(SPDR)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 16-2. SPI I/O Register Summary
Register.
SPRIE
SPRF
MC68HC908GR16 Data Sheet, Rev. 5.0
Bit 7
R7
T7
R
0
0
Register.) Through the SPSCK pin, the baud rate generator of the
= Reserved
ERRIE
Figure
R6
T6
R
6
0
0
NOTE
Figure 16-3
SPMSTR
16-4.
16.13.1 SPI Control
OVRF
R5
T5
5
1
0
MODF
CPOL
Unaffected by reset
shows the structure of the SPI module.
R4
T4
4
0
0
= Unimplemented
CPHA
SPTE
R3
T3
3
1
1
Register.
MODFEN
SPWOM
R2
T2
2
0
0
Functional Description
SPR1
SPE
R1
T1
1
0
0
SPTIE
SPR0
Bit 0
R0
T0
0
0
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