MC68HC908GR16VFJ Freescale Semiconductor, MC68HC908GR16VFJ Datasheet - Page 191

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MC68HC908GR16VFJ

Manufacturer Part Number
MC68HC908GR16VFJ
Description
IC MCU 16K FLASH 8MHZ SPI 32LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908GR16VFJ

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908GR16VFJ
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
15.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register
(MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down
to 32. This is ideal for applications using canned oscillators that do not require long startup times from
stop mode.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
15-20
Freescale Semiconductor
shows stop mode recovery time from interrupt.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
To minimize stop current, all pins configured as inputs should be driven to
a 1 or 0.
CGMXCLK
Note: Previous data can be operand data or the STOP opcode, depending
CPUSTOP
RST
IDB
IAB
R/W
IDB
IAB
on the last instruction.
$A6
Figure 15-18. Wait Recovery from Internal Reset
STOP ADDR
$6E0B
$A6
Figure 15-19. Stop Mode Entry Timing
PREVIOUS DATA
MC68HC908GR16 Data Sheet, Rev. 5.0
$A6
STOP ADDR + 1
CYCLES
32
NOTE
NOTE
NEXT OPCODE
Figure 15-19
CYCLES
32
SAME
shows stop mode entry timing.
RST VCT H
SAME
RST VCT L
SAME
SAME
Low-Power Modes
Figure
191

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