MC68HC908GR16VFJ Freescale Semiconductor, MC68HC908GR16VFJ Datasheet - Page 66

• Manufacturer Part Number: MC68HC908GR16VFJ
• Description: IC MCU 16K FLASH 8MHZ SPI 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR16VFJ

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clock Generator Module (CGM)
4.3.7 Special Programming Exceptions
The programming method described in
exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for
these exceptions:
See
4.3.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
4.3.9 CGM External Connections
In its typical configuration, the CGM requires up to nine external components. Five of these are for the
crystal oscillator and two or four are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in
Figure 4-2
circuitry. The oscillator configuration uses five components:
The series resistor (R
crystal manufacturer’s data for more information regarding values for C1 and C2.
Figure 4-2
Routing should be done with great care to minimize signal cross talk and noise.
See
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4.3.8 Base Clock Selector
20.9 Clock Generation Module Characteristics
A 0 value for R or N is interpreted exactly the same as a value of 1.
A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
Crystal, X
Fixed capacitor, C
Tuning capacitor, C
Feedback resistor, R
Series resistor, R
Bypass capacitor, C
Filter network
shows only the logical representation of the internal components and may not represent actual
also shows the external components for the PLL:
1
S
) is included in the diagram to follow strict Pierce oscillator guidelines. Refer to the
S
1
2
BYP
B
(can also be a fixed capacitor)
Circuit.
MC68HC908GR16 Data Sheet, Rev. 5.0
4.3.6 Programming the PLL
for capacitor and resistor values.
does not account for three possible
Freescale Semiconductor
Figure
4-2.