MC68HC908JL8CP Freescale Semiconductor, MC68HC908JL8CP Datasheet - Page 69

• Manufacturer Part Number: MC68HC908JL8CP
• Description: IC MCU 8K FLASH 8MHZ 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing.
Figure 5-10
5.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first.
pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
Freescale Semiconductor
INTERRUPT
INTERRUPT
MODULE
MODULE
I BIT
I BIT
R/W
R/W
IDB
IDB
IAB
IAB
shows interrupt recovery timing.
Figure 5-11
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
DUMMY
DUMMY
demonstrates what happens when two interrupts are pending. If an interrupt is
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
CCR
Figure 5-10. Interrupt Recovery
SP – 1
SP – 3
Figure 5-9
A
SP – 2
SP – 2
.
X
X
Interrupt Entry
SP – 3
SP – 1
PC – 1[15:8] PC – 1[7:0] OPCODE
A
SP – 4
SP
CCR
VECT H
PC
V DATA H
VECT L
PC + 1
V DATA L
OPERAND
Figure 5-9
START ADDR
Exception Control
OPCODE
shows
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