MC68HC908JL8CP Freescale Semiconductor, MC68HC908JL8CP Datasheet - Page 98

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MC68HC908JL8CP

Manufacturer Part Number
MC68HC908JL8CP
Description
IC MCU 8K FLASH 8MHZ 28-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908JL8CP

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Monitor ROM (MON)
The coding example below is to perform a page erase, from $EF00–$EF3F. The Initialization subroutine
is the same as the coding example for PRGRNGE (see
ERARNGE
MAIN:
7.5.3 LDRNGE
LDRNGE is used to load the data array in RAM with data from a range of FLASH locations.
The start location of FLASH from where data is retrieved is specified by the address ADDRH:ADDRL and
the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can
be retrieved in one routine call is 128 bytes. The data retrieved from FLASH is loaded into the data array
in RAM. Previous data in the data array will be overwritten. User can use this routine to retrieve data from
FLASH that was previously programmed.
The coding example below is to retrieve 32 bytes of data starting from $EF00 in FLASH. The Initialization
subroutine is the same as the coding example for PRGRNGE (see
LDRNGE
MAIN:
98
BSR
:
:
LDHX
JSR
:
BSR
:
:
LDHX
JSR
:
Routine Name
Routine Description
Calling Address
Stack Used
Data Block Format
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
EQU
INITIALISATION
#FILE_PTR
ERARNGE
EQU
INITIALIZATION
#FILE_PTR
LDRNGE
$FCBE
$FF30
LDRNGE
Loads data from a range of locations
$FF30
9 bytes
Bus speed (BUS_SPD)
Data size (DATASIZE)
Starting address (ADDRH)
Starting address (ADDRL)
Data 1
Data N
Table 7-13. LDRNGE Routine
:
7.5.1
PRGRNGE).
7.5.1
PRGRNGE).
Freescale Semiconductor

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