MC68HC908JL8CP Freescale Semiconductor, MC68HC908JL8CP Datasheet - Page 76

• Manufacturer Part Number: MC68HC908JL8CP
• Description: IC MCU 8K FLASH 8MHZ 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

System Integration Module (SIM)
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit
clears it.
5.7.2 Reset Status Register (RSR)
This register contains six flags that show the source of the last reset. Clear the SIM reset status register
by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
POR — Power-On Reset Bit
76
;
;
;
;
This code works if the H register has been pushed onto the stack in the break
service routine software. This code should be executed at the end of the
break service routine software.
HIBYTE
LOBYTE
DOLO
RETURN
This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break
interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
1 = Last reset caused by POR circuit
0 = Read of RSR
EQU
EQU
If not SBSW, do RTI
BRCLR
TST
BNE
DEC
DEC
PULH
RTI
Address:
Read:
Write:
POR:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
5
6
SBSW,BSR, RETURN
LOBYTE,SP
DOLO
HIBYTE,SP
LOBYTE,SP
$FE01
POR
Bit 7
1
Figure 5-21. Reset Status Register (RSR)
= Unimplemented
PIN
6
0
COP
5
0
;
;
; If RETURNLO is not zero,
; then just decrement low byte.
; Else deal with high byte, too.
; Point to WAIT/STOP opcode.
; Restore H register.
See if wait mode or stop mode was exited
by break.
ILOP
4
0
ILAD
3
0
MODRST
2
0
LVI
1
0
Freescale Semiconductor
Bit 0
0
0