MC68HC908SR12CB Freescale Semiconductor, MC68HC908SR12CB Datasheet - Page 129

• Manufacturer Part Number: MC68HC908SR12CB
• Description: IC MCU 12K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 29
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
NOTE:
PLLON — PLL On Bit
BCS — Base Clock Select Bit
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMPCLK requires two writes to the PLL control
register. (See
PRE1 and PRE0 — Prescaler Program Bits
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
This read/write bit selects either the oscillator output, CGMXCLK, or
the divided VCO clock, CGMPCLK, as the source of the CGM output,
CGMOUT. CGMOUT frequency is one-half the frequency of the
selected clock. BCS cannot be set while the PLLON bit is clear. After
toggling BCS, it may take up to three CGMXCLK and three
CGMPCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. (See
Base Clock Selector
These read/write bits control a prescaler that selects the prescaler
power-of-two multiplier, P. (See
Programming the
the PLLON bit is set. Reset clears these bits.
These prescaler bits affects the relationship between the VCO clock
and the final system bus clock.
1 = PLL on
0 = PLL off
1 = CGMPCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
Clock Generator Module (CGM)
8.4.8 Base Clock Selector
PLL.) PRE1 and PRE0 cannot be written when
Circuit.) Reset clears the BCS bit.
8.4.3 PLL Circuits
8.4.8 Base Clock Selector
Circuit.)
Clock Generator Module (CGM)
and
CGM Registers
8.4.6
Data Sheet
8.4.8
129