MC68HC908SR12CB Freescale Semiconductor, MC68HC908SR12CB Datasheet - Page 170

• Manufacturer Part Number: MC68HC908SR12CB
• Description: IC MCU 12K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 29
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Monitor ROM (MON)
Data Sheet
170
NOTE:
If V
(above condition set 1), the bus frequency is a divide-by-two of the input
clock. If PTC1 is high with V
entry, the bus frequency will be a divide-by-four of the input clock.
Holding the PTC1 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator only if V
In this event, the CGMOUT frequency is equal to the CGMXCLK
frequency, and the OSC1 input directly generates internal bus clocks. In
this case, the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
If entering monitor mode without high voltage on IRQ1 (above condition
set 2 or 3, where applied voltage is either V
requirements and conditions, including the PTC1 frequency divisor
selection, are not in effect. This is to reduce circuit requirements when
performing in-circuit programming.
If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial POR reset. Once the part has
been programmed, the traditional method of applying a voltage, V
IRQ1 must be used to enter monitor mode.
The COP module is disabled in monitor mode based on these
conditions:
The second condition states that as long as V
IRQ1 pin after entering monitor mode, or if V
the initial reset to get into monitor mode (when V
IRQ1), then the COP will be disabled. In the latter situation, after V
applied to the RST pin, V
interest of freeing the IRQ1 for normal functionality in monitor mode.
•
•
TST
If monitor mode was entered as a result of the reset vector being
blank (above condition set 2 or 3), the COP is always disabled
regardless of the state of IRQ1 or RST.
If monitor mode was entered with V
then the COP is disabled as long as V
or RST.
is applied to IRQ1 and PTC1 is low upon monitor mode entry
Monitor ROM (MON)
TST
TST
can be removed from the IRQ1 pin in the
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
applied to IRQ1 upon monitor mode
TST
DD
TST
TST
on IRQ1 (condition set 1),
or V
TST
is applied to either IRQ1
TST
is applied to RST after
TST
SS
is maintained on the
Freescale Semiconductor
), then all port A pin
is applied to IRQ1.
was applied to
TST
TST
, to
is