MC68HC908SR12CB Freescale Semiconductor, MC68HC908SR12CB Datasheet - Page 305

• Manufacturer Part Number: MC68HC908SR12CB
• Description: IC MCU 12K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 29
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.7.4 MMIIC Status Register (MMSR)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
Address:
MMRXIF — MMIIC Receive Interrupt Flag
MMTXIF — MMIIC Transmit Interrupt Flag
MMATCH — MMIIC Address Match Flag
Reset:
Read: MMRXIF
Write:
This flag is set after the data receive register (MMDRR) is loaded with
a new received data. Once the MMDRR is loaded with received data,
no more received data can be loaded to the MMDRR register until the
CPU reads the data from the MMDRR to clear MMRXBF flag.
MMRXIF generates an interrupt request to CPU if the MMIEN bit in
MMCR is also set. This bit is cleared by writing "0" to it or by reset; or
when the MMEN = 0.
This flag is set when data in the data transmit register (MMDTR) is
downloaded to the output circuit, and that new data can be written to
the MMDTR. MMTXIF generates an interrupt request to CPU if the
MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it
or when the MMEN = 0.
This flag is set when the received data in the data receive register
(MMDRR) is a calling address which matches with the address or its
extended addresses (MMEXTAD = 1) specified in the address
register (MMADR). The MMATCH flag is set at the 9th clock of the
calling address and will be cleared on the 9th clock of the next
receiving data. Note: slave transmits do not clear MMATCH.
1 = New data in data receive register (MMDRR)
0 = No data received
1 = Data transfer completed
0 = Data transfer in progress
$004B
Bit 7
Multi-Master IIC Interface (MMIIC)
0
0
Figure 17-7. MMIIC Status Register (MMSR)
= Unimplemented
MMTXIF MMATCH MMSRW MMRXAK
6
0
0
5
0
4
0
3
1
Multi-Master IIC Interface (MMIIC)
MMCRCBF
2
0
MMIIC I/O Registers
MMTXBE MMRXBF
1
1
Data Sheet
Bit 0
0
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