MC68HC11E1CFNE2 Freescale Semiconductor, MC68HC11E1CFNE2 Datasheet - Page 87

• Manufacturer Part Number: MC68HC11E1CFNE2
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 38
• Interface: SCI/SPI
• Memory Type: ROM
• Number Of Bits: 8
• Package Type: 52-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 2MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

5.5 Interrupts
The MCU has 18 interrupt vectors that support 22 interrupt sources. The 15 maskable interrupts are
generated by on-chip peripheral systems. These interrupts are recognized when the global interrupt mask
bit (I) in the condition code register (CCR) is clear. The three non-maskable interrupt sources are illegal
opcode trap, software interrupt, and XIRQ pin. Refer to
vector assignments for each source.
For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the
normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system is
cleared by the automatic clearing mechanism consisting of a read of the SCI status register while RDRF
is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt request
would be to read the SCI status register to check for receive errors, then to read the received data from
the SCI data register. These steps satisfy the automatic clearing mechanism without requiring special
instructions.
Freescale Semiconductor
PSEL[3:0]
Table 5-3. Highest Priority Interrupt Selection
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
M68HC11E Family Data Sheet, Rev. 5.1
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
SCI serial system
Reserved (default to IRQ)
IRQ (external pin or parallel I/O)
Real-time interrupt
Timer input capture 1
Timer input capture 2
Timer input capture 3
Timer output compare 1
Timer output compare 2
Timer output compare 3
Timer output compare 4
Timer input capture 4/output compare 5
Interrupt Source Promoted
Table
5-4, which shows the interrupt sources and
Interrupts
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