ATAB5423-3-WB Atmel, ATAB5423-3-WB Datasheet - Page 54

• Manufacturer Part Number: ATAB5423-3-WB
• Description: KIT DEMO 315MHZ BLACKBIRD
• Manufacturer: Atmel
• Type: Transceiver, UHFr

Specifications of ATAB5423-3-WB

• Frequency: 315MHz
• Product: RF Modules
• For Use With/related Products: ATA5423
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATAB-5423-3-WB

Figure 9-1.
54
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.
Output level on pin RX_ACTIVE
T
Start-up mode:
Bit-check mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,
the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to
receiving mode. Otherwise it is set to Sleep mode or to Start_up mode.
Output level on pin RX_ACTIVE
I
Receiving mode:
The incomming data stream is passed via the TX/RX Data Buffer to the connected
microcontroller. If an bit error occurs the transceiver is set back to Start-up mode.
Output level on pin RX_ACTIVE
I
S
S
Sleep
= I
= I
ATA5423/ATA5425/ATA5428/ATA5429
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE
RX_X
RX_X
= Sleep
Start RX Mode
NO
; T
Flow Chart Polling Mode/RX Mode (T_MODE = 0, Transparent Mode Inactive)
Bit-check
1024
T
OPM0 = 1
SLEEP
?
?
T
DCLK
YES
YES
= 0
Start RX Polling Mode
X
Sleep
written into the TX/RX
Low; I
High
High
RX data stream is
YES
NO
High; I
High; I
Data Buffer
detected ?
Bit error ?
S
Start bit
= I
NO
NO
S
S
IDLE_X
= I
= I
Startup_PLL_X
RX_X
YES
Set VSOUT_EN = 1
Set CLK_ON = 1
Set OPM0 = 1
; T
P_MODE = 0
Bit check
Startup_Sig_proc
Set IRQ
OK ?
NO
NO
?
; I
YES
YES
Startup_PLL
Sleep:
X
T
T
T
T
DCLK
Startup_PLL
Startup_Sig_Proc
Bit-check
Sleep
:
:
:
:
:
Defined by bits Sleep 0 to Sleep 4 in Control
Register 4
Defined by bit XSleep in Control register 4
Basic clock cycle
798.5
882
498
306
210
Is defined by the selected baud rate range and
T
Baud 0 and Baud 1 in Control Register 6.
Depends on the result of the bit check.
If the bit check is ok, T
number of bits to be checked (N
on the utilized data rate.
If the bit check fails, the average time period for
that check despends on the selected bit-rate
range and on T
defined by bit Baud 0 and Baud 1 in Control
Register 6.
If the transceiver detects a bit errror after a
successful bit check and before the start bit is
detected pin IRQ will be set to high (only if
P_MODE = 0) and the transceiver is set back to
start-up mode.
DCLK
T
T
T
T
.The baud-rate range is defined by bit
DCLK
DCLK
DCLK
DCLK
T
DCLK
(typ)
XDCLK
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
. The bit-rate range is
Bit-check
4841D–WIRE–10/07
depends on the
Bit-check
) and