T48C862M-R3-TNS Atmel, T48C862M-R3-TNS Datasheet - Page 20

• Manufacturer Part Number: T48C862M-R3-TNS
• Description: IC MON TIRE PRESS 315MHZ 24SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R3-TNS

• Frequency: 315MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Table 1. Interrupt Priority
Table 2. Hardware Interrupts
Software Interrupts
Hardware Interrupts
20
Interrupt
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
Interrupt
INT1
INT2
INT3
INT4
INT5
INT6
INT7
T48C862-R3
Priority
Highest
Lowest
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Register
T3CM1
T3CM2
P5CR
T2CM
P5CR
SISC
VCM
T1M
T3C
The programmer can generate interrupts by using the software interrupt instruction
(SWI), which is supported in qFORTH by predefined macros named SWI0...SWI7. The
software triggered interrupt operates exactly like any hardware triggered interrupt. The
SWI instruction takes the top two elements from the expression stack and writes the cor-
responding bits via the I/O bus to the interrupt pending register. Therefore, by using the
SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for
later execution.
In the microcontroller block, there are eleven hardware interrupt sources with seven
different levels. Each source can be masked individually by mask bits in the correspond-
ing control registers. An overview of the possible hardware configurations is shown in
Table 3.
ROM Address
0C0h
1C0h
1E0h
040h
080h
100h
140h
180h
Interrupt Mask
D8h (SCALL 0C0h)
FCh (SCALL 1E0h)
F8h (SCALL 1C0h)
C8h (SCALL 040h)
D0h (SCALL 080h)
E8h (SCALL 100h)
E8h (SCALL 140h)
F0h (SCALL 180h)
Interrupt Opcode
P52M1, P52M2
P53M1, P53M2
P50M1, P50M2
P51M1, P51M2
T3EIM
T3IM1
T3IM2
T1IM
T2IM
SIM
VIM
Bit
Function
Software interrupt (SWI0)
External hardware interrupt, any edge at BP52 or
BP53
Timer 1 interrupt
SSI interrupt or external hardware interrupt at BP40
or BP43
Timer 2 interrupt
Timer 3 interrupt
External hardware interrupt, at any edge at BP50 or
BP51
Voltage monitor (VM) interrupt
Interrupt Source
Any edge at BP52
any edge at BP53
Timer 1
SSI buffer full/empty or BP40/BP43 interrupt
Timer 2 compare match/overflow
Timer 3 compare register 1 match
Timer 3 compare register 2 match
Timer 3 edge event occurs (T3I)
Any edge at BP50,
any edge at BP51
External/internal voltage monitoring
4554A–4BMCU–02/03