T48C862M-R3-TNS Atmel, T48C862M-R3-TNS Datasheet - Page 73

• Manufacturer Part Number: T48C862M-R3-TNS
• Description: IC MON TIRE PRESS 315MHZ 24SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R3-TNS

• Frequency: 315MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

MCL Bus Protocol
4554A–4BMCU–02/03
The MCL protocol constitutes a simple 2-wire bi-directional communication highway via
which devices can communicate control and data information. Although the MCL proto-
col can support multi-master bus configurations, the SSI in MCL mode is intended for
use purely as a master controller on a single master bus system. So all reference to
multiple bus control and bus contention will be omitted at this point.
All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit.
Normally the communication channel is opened with a so-called start condition, which
initializes all devices connected to the bus. This is then followed by a data telegram,
transmitted by the master controller device. This telegram usually contains an 8-bit
address code to activate a single slave device connected onto the MCL bus. Each slave
receives this address and compares it with its own unique address. The addressed
slave device, if ready to receive data, will respond by pulling the SD line low during the
9th clock pulse. This represents a so-called MCL acknowledge. The controller detecting
this affirmative acknowledge then opens a connection to the required slave. Data can
then be passed back and forth by the master controller, each 8-bit telegram being
acknowledged by the respective recipient. The communication is finally closed by the
master device and the slave device put back into standby by applying a stop condition
onto the bus.
Figure 70. MCL Bus Protocol 1
Bus not busy (1)
Start data transfer (2)
Stop data transfer (3)
Data valid (4)
Acknowledge
SC
SD
(1)
condition
Start
(2)
Both data and clock lines remain HIGH.
A HIGH to LOW transition of the SD line while the clock (SC)
is HIGH defines a START condition
A LOW to HIGH transition of the SD line while the clock (SC)
is HIGH defines a STOP condition.
The state of the data line represents valid data when,
after START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
All address and data words are serially transmitted to and
from the device in eight-bit words. The receiving device
returns a zero on the data line during the ninth clock cycle to
acknowledge word receipt.
valid
Data
(4)
change
Data
valid
Data
(4)
T48C862-R3
condition
Stop
(3)
(1)
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