T48C862M-R3-TNS Atmel, T48C862M-R3-TNS Datasheet - Page 53

• Manufacturer Part Number: T48C862M-R3-TNS
• Description: IC MON TIRE PRESS 315MHZ 24SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R3-TNS

• Frequency: 315MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Timer 2 Compare and
Compare Mode Registers
Timer 2 Compare Mode
Register (T2CM)
Timer 2 COmpare Register 1
(T2CO1)
4554A–4BMCU–02/03
Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for
the 8-bit stage of Timer 2. The timer compares the contents of the compare register cur-
rent counter value and if it matches it generates an output signal. Dependent on the
timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop
as SSI clock or as a clock for the next counter stage.
In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit
compare value. In all other modes, the two compare registers work independently as a
4- and 8-bit compare register.
When assigned to the compare register a compare event will be suppressed.
In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
Timer 2 Output Mode
1, 2, 3, 4, 5 and 6
1, 2, 3, 4, 5 and 6
7
T2OTM
T2CTM
T2RM
T2IM
Write cycle
T2OTM
Bit 3
Timer 2 Overflow Toggle Mask bit
T2OTM = 0, disable overflow toggle
T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output
Timer 2 Compare Toggle Mask bit
T2CTM = 0, disable compare toggle
T2CTM = 1, enable compare toggle, a match of the counter with the compare
Timer 2 Reset Mask bit
T2RM = 0, disable counter reset
T2RM = 1, enable counter reset, a match of the counter with the compare register
Timer 2 Interrupt Mask bit
T2IM = 0, disable Timer 2 interrupt
T2IM = 1, enable Timer 2 interrupt
T2CTM
Bit 2
Bit 3
flip-flop (TOG2). If the T2OTM-bit is set, only a counter overflow can
generate an interrupt except on the Timer 2 output mode 7.
register toggles output flip-flop (TOG2). In Timer 2 output mode 7 and
when the T2CTM-bit is set, only a match of the counter with the
compare register can generate an interrupt.
resets the counter
T2RM
Bit 1
T2OTM
Bit 2
0
1
x
T2IM
Bit 0
Bit 1
T2CTM
1
x
x
Address: "7"hex - Subaddress: "3"hex
Address: "7"hex - Subaddress: "4"hex
Bit 0
Timer 2 Interrupt Source
Compare match (CM2)
Overflow (OVF2)
Compare match (CM2)
T48C862-R3
Reset value: 0000b
Reset value: 1111b
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