MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet
MFRC50001T/0FE,112
Specifications of MFRC50001T/0FE,112
935268039112
MFRC500
MFRC51T0FED
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MFRC50001T/0FE,112 Summary of contents
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MFRC500 Highly Integrated ISO/IEC 14443 A Reader IC Rev. 3.3 — 15 March 2010 048033 1. Introduction This data sheet describes the functionality of the MFRC500 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system ...
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... NXP Semiconductors 3. Features and benefits 3.1 General Highly integrated analog circuitry for demodulating and decoding card response Buffered output drivers enable antenna connection using the minimum of external components Proximity operating distance up to 100 mm Supports the ISO/IEC 14443 A standard, parts Supports MIFARE Classic protocol ...
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... NXP Semiconductors 5. Quick reference data Table 1. Quick reference data Symbol Parameter T ambient temperature amb T storage temperature stg V digital supply voltage DDD V analog supply voltage DDA V TVDD supply voltage DD(TVDD input voltage (absolute i value) I input leakage current LI I TVDD supply current DD(TVDD) 6 ...
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... NXP Semiconductors 7. Block diagram NWR NRD NCS ALE PARALLEL INTERFACE CONTROL (INCLUDING AUTOMATIC INTERFACE DETECTION AND SYNCHRONISATION) FIFO CONTROL 64-BYTE FIFO CONTROL REGISTER BANK EEPROM 32 × 16-BYTE ACCESS EEPROM CONTROL MASTER KEY BUFFER CRYPTO1 UNIT 32-BIT PSEUDO RANDOM GENERATOR AMPLITUDE RATING ...
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... NXP Semiconductors 8. Pinning information Fig 2. 8.1 Pin description Table 3. Pin description Pin Symbol Type 1 OSCIN I 2 IRQ O 3 MFIN I [2] 4 MFOUT O 5 TX1 O 6 TVDD P 7 TX2 O 8 TVSS G 9 NCS I [3] 10 NWR I R/NW I nWrite I [3] 11 NRD I NDS I nDStrb I MFRC500_33 Product data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued Pin Symbol Type 12 DVSS G [ I/O AD0 to AD7 I/O [3] 21 ALE nAStrb I [ nWait [ DVDD P 26 AVDD P 27 AUX O 28 AVSS VMID P 31 RSTPD I 32 OSCOUT O [1] Pin types Input Output, I/O = Input/Output Power and G = Ground. [2] The SLRC400 uses pin name SIGOUT for pin MFOUT. The MFRC500 functionality includes test functions for the SLRC400 using pin MFOUT ...
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... NXP Semiconductors 9. Functional description 9.1 Digital interface 9.1.1 Overview of supported microprocessor interfaces The MFRC500 supports direct interfacing to various 8-bit microprocessors. Alternatively, the MFRC500 can be connected to a PC’s Enhanced Parallel Port (EPP). the parallel interface signals supported by the MFRC500. Table 4. Bus control signals ...
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... NXP Semiconductors 9.1.3 Connection to different microprocessor types The connection to various microprocessor types is shown in Table 5. MFRC500 pins ALE NRD NWR NCS 9.1.3.1 Separate read and write strobe address bus (A3 to An) ADDRESS DECODER address bus (A0 to A2) data bus (D0 to D7) HIGH Read strobe (NRD) Write strobe (NWR) Fig 3 ...
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... NXP Semiconductors 9.1.3.2 Common read and write strobe address bus (A3 to An) ADDRESS DECODER address bus (A0 to A2) data bus (D0 to D7) HIGH Data strobe (NDS) Read/Write (R/NW) Fig 4. Connection to microprocessor: common read and write strobes Refer to 9.1.3.3 Common read and write strobe: EPP with handshake Fig 5 ...
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... NXP Semiconductors 9.2 Memory organization of the EEPROM Table 6. Block Position MFRC500_33 Product data sheet PUBLIC EEPROM memory organization diagram Byte address Access Memory content Address 0 00h to 0Fh R 1 10h to 1Fh R/W 2 20h to 2Fh R/W 3 30h to 3Fh R/W 4 40h to 4Fh R/W 5 50h to 5Fh ...
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... NXP Semiconductors 9.2.1 Product information field (read only) Table 7. Byte Symbol Access Table 8. Byte Internal Table 9. Definition Byte Value [1] Byte 4 contains the current version number. 9.2.2 Register initialization files (read/write) Register initialization from address 10h to address 2Fh is performed automatically during the initializing phase (see initialization file ...
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... NXP Semiconductors The byte assignment is shown in Table 10. EEPROM byte address 10h (block 1, byte 0) 11h … 2Fh (block 2, byte 15) 9.2.2.2 Factory default StartUp register initialization file During the production tests, the StartUp register initialization file is initialized using the default values shown in values are written to the MFRC500’s registers. ...
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... NXP Semiconductors Table 11. Shipment content of StartUp configuration file EEPROM Register Value Symbol byte address address 29h 29h 08h FIFOLevel 2Ah 2Ah 07h TimerClock 2Bh 2Bh 06h TimerControl 2Ch 2Ch 0Ah TimerReload 2Dh 2Dh 02h IRQPinConfig 2Eh 2Eh 00h PreSet2E 2Fh 2Fh ...
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... NXP Semiconductors Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is shown in Master key byte 0 (LSB) Master key bits EEPROM byte n address 5Ah Example Fig 6. Key storage format Example: The value for the key must be written to the EEPROM. ...
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... NXP Semiconductors When the microprocessor starts a command, the MFRC500 can still access the FIFO buffer while the command is running. Only one FIFO buffer has been implemented which is used for input and output. Therefore, the microprocessor must ensure that there are no inadvertent FIFO buffer accesses. ...
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... NXP Semiconductors HiAlert The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or less are stored in the FIFO buffer. The trigger is generated by LoAlert 9.3.4 FIFO buffer registers and flags Table 14 Table 14. Flags FIFOLength[6:0] FIFOOvfl FlushFIFO HiAlert HiAlertIEn HiAlertIRq ...
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... NXP Semiconductors When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see Section 9.3.3 on page logic 1. When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see Section 9.3.3 Table 15. Interrupt flag TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq 9 ...
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... NXP Semiconductors Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0 while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq to logic 1 and leaves all other bits unchanged. 9.4.3 Configuration of pin IRQ The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be controlled using the following IRQPinConfig register bits. • ...
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... NXP Semiconductors 9.5 Timer unit The timer derives its clock from the 13.56 MHz on-board chip clock. The microprocessor can use this timer to manage timing-relevant tasks. The timer unit may be used in one of the following configurations: • Timeout counter • WatchDog counter • ...
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... NXP Semiconductors Fig 7. The timer unit is designed, so that events when combined with enabling flags start or stop the counter. For example, setting bit TStartTxBegin = logic 1 enables control of received data with the timer unit. In addition, the first received bit is indicated by the TxBegin event. ...
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... NXP Semiconductors • transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic 1 • transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd = logic 1 • bit TStartNow is set to logic 1 by the microprocessor Remark: Every start event reloads the timer from the TimerReload register which re-triggers the timer unit ...
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... NXP Semiconductors 9.5.2 Using the timer unit functions 9.5.2.1 Time-out and WatchDog counters After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue register beginning with a given start event given stop event occurs, such as a bit being received from the card, the timer unit stops without generating an interrupt. ...
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... NXP Semiconductors 9.5.3 Timer unit registers Table 18 Table 18. Flags TAutoRestart TimerValue[7:0] TReloadValue[7:0] TPreScaler[4:0] TRunning TStartNow TStartTxBegin TStartTxEnd TStopNow TStopRxBegin TStopRxEnd 9.6 Power reduction modes 9.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself) ...
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... NXP Semiconductors Table 19. Symbol RX VMID RSTPD OSCOUT 9.6.2 Soft power-down mode Soft power-down mode is entered immediately using the Control register bit PowerDown. All internal current sinks, including the oscillator buffer, are switched off. The digital input buffers are not separated from the input pads and keep their functionality. In addition, the digital output pins do not change their state ...
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... NXP Semiconductors 9.7 StartUp phase The events executed during the StartUp phase are shown in Fig 8. 9.7.1 Hard power-down phase The hard power-down phase is active during the following cases: • a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated when V • a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level period on pin RSTPD must be at least 100 μ ...
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... NXP Semiconductors To ensure correct detection of the microprocessor interface, the following sequence is executed: • the Command register is read until the 6-bit register value is 00h. On reading the 00h value, the internal initialization phase is complete and the MFRC500 is ready to be controlled • write 80h to the Page register to initialize the microprocessor interface • ...
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... NXP Semiconductors 9.9 Transmitter pins TX1 and TX2 The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly, using minimal passive components for matching and filtering (see output circuitry is designed with a very low-impedance source resistance. The TxControl register is used to control the TX1 and TX2 signals ...
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... NXP Semiconductors 9.9.2 Antenna operating distance versus power consumption Using different antenna matching circuits (by varying the supply voltage on the antenna driver supply pin TVDD possible to find the trade-off between maximum effective operating distance and power consumption. Different antenna matching circuits are described in the Application note “ ...
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... NXP Semiconductors Table 22. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod MANT = Mantissa; EXP= Exponent. GsCfgCW, EXP , MANT GsCfgCW GsCfgMod EXP MANT GsCfgMod (decimal) (decimal) (decimal 9.9.3.2 Calculating the relative source resistance The reference source resistance ref The reference source resistance (R using ModConductance register’ ...
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... NXP Semiconductors 9.9.4 Pulse width The envelope carries the data signal information that is transmitted to the card encoded data signal based on the Miller code. In addition, each pause of the Miller encoded signal is again encoded as a pulse of a fixed width. The width of the pulse is adjusted using the ModWidth register ...
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... NXP Semiconductors The signal can be observed on its way through the receiver as shown in signal at a time can be routed to pin AUX using the TestAnaSelect register as described in Section 15.2.2 on page 9.10.2 Receiver operation In general, the default settings programmed in the StartUp initialization file are suitable for use with the MFRC500 to MIFARE card data communication ...
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... NXP Semiconductors 9.10.2.2 Amplifier The demodulated signal must be amplified by the variable amplifier to achieve the best performance. The gain of the amplifiers can be adjusted using the RxControl1 register Gain[1:0] bits; see Table 23. See Table 78 “RxControl1 register bit descriptions” on page 55 Register setting 00 01 ...
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... NXP Semiconductors Remark recommended to use the Q-clock. 9.11 Serial signal switch The MFRC500 comprises two main blocks: • digital circuitry: comprising the state machines, encoder and decoder logic etc. • analog circuitry: comprising the modulator, antenna drivers, receiver and amplification circuitry The interface between these two blocks can be configured so that the interface signals are routed to pins MFIN and MFOUT ...
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... NXP Semiconductors Section settings used to configure and control the serial signal switch. 9.11.2 Serial signal switch registers The RxControl2 register DecoderSource[1:0] bits define the input signal for the internal Manchester decoder and are described in Table 24. See Table 88 on page 57 Number The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the transmitted 13 ...
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... NXP Semiconductors Remark: To use the MFOUTSelect[2:0] bits, the TestDigiSelect register SignalToMFOUT bit must be logic 0. 9.11.2.1 Active antenna concept The MFRC500 analog and digital circuitry is accessed using pins MFIN and MFOUT. Table 27 Table 27. Register Analog circuitry settings ModulatorSource MFOUTSelect DecoderSource Digital circuitry settings ...
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... NXP Semiconductors 9.12.1 Crypto1 key handling On execution of the authentication command, the MFRC500 reads the key from the key buffer. The key is always read from the key buffer and ensures Crypto1 authentication commands do not require addressing of a key. The user must ensure the correct key is prepared in the key buffer before triggering card authentication ...
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... NXP Semiconductors 10. MFRC500 registers 10.1 Register addressing modes Three methods can be used to operate the MFRC500: • initiating functions and controlling data by executing commands • configuring the functional operation using a set of configuration bits • monitoring the state of the MFRC500 by reading status flags The commands, configuration bits and flags are accessed using the microprocessor interface ...
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... NXP Semiconductors 10.2 Register bit behavior Bits and flags for different registers behave differently, depending on their functions. In principle, bits with same behavior are grouped in common registers. the function of the Access column in the register tables. Table 30. Abbreviation R MFRC500_33 Product data sheet PUBLIC ...
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... NXP Semiconductors 10.3 Register overview Table 31. MFRC500 register overview Sub Register name address (Hex) Page 0: Command and status 00h Page 01h Command 02h FIFOData 03h PrimaryStatus 04h FIFOLength 05h SecondaryStatus 06h InterruptEn 07h InterruptRq Page 1: Control and status 08h Page 09h ...
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... NXP Semiconductors Table 31. MFRC500 register overview Sub Register name address (Hex) Page 4: RF Timing and channel redundancy 20h Page 21h RxWait 22h ChannelRedundancy 23h CRCPresetLSB 24h CRCPresetMSB 25h PreSet25 26h MFOUTSelect 27h PreSet27 Page 5: FIFO, timer and IRQ pin configuration 28h ...
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... NXP Semiconductors 10.4 MFRC500 register flags overview Table 32. Flag(s) AccessErr BitPhase[7:0] ClkQ180Deg ClkQCalib ClkQDelay[4:0] CollErr CollLevel[3:0] CollPos[7:0] Command[5:0] CRC3309 CRC8 CRCErr CRCPresetLSB[7:0] CRCPresetMSB[7:0] CRCReady CRCResultMSB[7:0] CRCResultLSB[7:0] Crypto1On DecoderSource[1:0] E2Ready Err FIFOData[7:0] FIFOLength[6:0] FIFOOvfl FlushFIFO FramingErr Gain[1:0] GsCfgCW[5:0] HiAlert HiAlertIEn HiAlertIRq IdleIEn ...
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... NXP Semiconductors Table 32. Flag(s) LoAlertIEn LoAlertIRq MFOUTSelect[2:0] MinLevel[3:0] ModemState[2:0] ModulatorSource[1:0] ModWidth[7:0] PageSelect[2:0] ParityEn ParityErr ParityOdd PowerDown RcvClkSelI RxAlign[2:0] RxAutoPD RxCRCEn RxIEn RxIRq RxLastBits[2:0] RxMultiple RxWait[7:0] SetIEn SetIRq SignalToMFOUT StandBy TAutoRestart TestAnaOutSel[4:0] TestDigiSignalSel[6:0] TimerIEn TimerIRq TimerValue[7:0] TPreScaler[4:0] TReloadValue[7:0] TRunning TStartTxBegin TStartTxEnd TStartNow ...
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... NXP Semiconductors Table 32. Flag(s) TX1RFEn TX2Cw TX2Inv TX2RFEn TxCRCEn TxIEn TxIRq TxLastBits[2:0] UsePageSelect WaterLevel[5:0] ZeroAfterColl 10.5 Register descriptions 10.5.1 Page 0: Command and status 10.5.1.1 Page register Selects the page register. Table 33. Bit Symbol Access Table 34. Bit MFRC500_33 Product data sheet PUBLIC ...
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... NXP Semiconductors 10.5.1.2 Command register Starts and stops the command execution. Table 35. Bit Symbol Access Table 36. Bit 10.5.1.3 FIFOData register Input and output of the 64 byte FIFO buffer. Table 37. Bit Symbol Access Table 38. Bit MFRC500_33 Product data sheet PUBLIC Command register (address: 01h) reset value: x000 0000b, x0h bit allocation ...
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... NXP Semiconductors 10.5.1.4 PrimaryStatus register Bits relating to receiver, transmitter and FIFO buffer status flags. Table 39. Bit Symbol Access Table 40. Bit Symbol ModemState[2:0] 3 IRq 2 Err 1 HiAlert 0 LoAlert MFRC500_33 Product data sheet PUBLIC PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation ...
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... NXP Semiconductors 10.5.1.5 FIFOLength register Number of bytes in the FIFO buffer. Table 41. Bit Symbol Access Table 42. Bit Symbol FIFOLength[6:0] 10.5.1.6 SecondaryStatus register Various secondary status flags. Table 43. Bit Symbol Access Table 44. Bit Symbol 7 TRunning 6 E2Ready 5 CRCReady RxLastBits[2:0] MFRC500_33 Product data sheet PUBLIC ...
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... NXP Semiconductors 10.5.1.7 InterruptEn register Control bits to enable and disable passing of interrupt requests. Table 45. Bit Symbol Access Table 46. Bit Symbol 7 SetIEn TimerIEn 4 TxIEn 3 RxIEn 2 IdleIEn 1 HiAlertIEn - 0 LoAlertIEn - [1] This bit can only be set or cleared using bit SetIEn. 10.5.1.8 InterruptRq register Interrupt request flags. ...
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... NXP Semiconductors Table 48. Bit Symbol 2 IdleIRq 1 HiAlertIRq 0 LoAlertIRq [1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq. 10.5.2 Page 1: Control and status 10.5.2.1 Page register Selects the page register; see 10.5.2.2 Control register Various control flags, for timer, power saving, etc. ...
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... NXP Semiconductors 10.5.2.3 ErrorFlag register Error flags show the error status of the last executed command. Table 51. Bit Symbol Access Table 52. Bit Symbol KeyErr 5 AccessErr 4 FIFOOvfl 3 CRCErr 2 FramingErr 1 ParityErr 0 CollErr MFRC500_33 Product data sheet PUBLIC ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation ...
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... NXP Semiconductors 10.5.2.4 CollPos register Bit position of the first bit-collision detected on the RF interface. Table 53. Bit Symbol Access Table 54. Bit 10.5.2.5 TimerValue register Value of the timer. Table 55. Bit Symbol Access Table 56. Bit 10.5.2.6 CRCResultLSB register LSB of the CRC coprocessor register. Table 57. ...
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... NXP Semiconductors 10.5.2.7 CRCResultMSB register MSB of the CRC coprocessor register. Table 59. Bit Symbol Access Table 60. Bit 10.5.2.8 BitFraming register Adjustments for bit oriented frames. Table 61. Bit Symbol Access Table 62. Bit Symbol RxAlign[2: TxLastBits[2:0] MFRC500_33 Product data sheet PUBLIC CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit ...
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... NXP Semiconductors 10.5.3 Page 2: Transmitter and control 10.5.3.1 Page register Selects the page register; see 10.5.3.2 TxControl register Controls the logical behavior of the antenna pins TX1 and TX2. Table 63. Bit Symbol Access Table 64. Bit MFRC500_33 Product data sheet PUBLIC Section 10.5.1.1 “Page register” on page ...
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... NXP Semiconductors 10.5.3.3 CwConductance register Selects the conductance of the antenna driver pins TX1 and TX2. Table 65. Bit Symbol Access Table 66. Bit See Section 9.9.3.1 10.5.3.4 PreSet13 register These bit settings must not be changed. Table 67. Bit Symbol Access Table 68. Bit 10.5.3.5 PreSet14 register These bit settings must not be changed ...
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... NXP Semiconductors 10.5.3.6 ModWidth register Selects the pulse-modulation width. Table 71. Bit Symbol Access Table 72. Bit 10.5.3.7 PreSet16 register These bit settings must not be changed. Table 73. Bit Symbol Access Table 74. Bit Symbol 00000000 10.5.3.8 PreSet17 register These bit settings must not be changed. ...
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... NXP Semiconductors 10.5.4 Page 3: Receiver and decoder control 10.5.4.1 Page register Selects the page register; see 10.5.4.2 RxControl1 register Controls receiver operation. Table 77. Bit Symbol Access Table 78. Bit Symbol 111 Gain[1:0] 10.5.4.3 DecoderControl register Controls decoder operation. Table 79. Bit Symbol Access Table 80 ...
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... NXP Semiconductors 10.5.4.4 BitPhase register Selects the bit-phase between transmitter and receiver clock. Table 81. Bit Symbol Access Table 82. Bit 10.5.4.5 RxThreshold register Selects thresholds for the bit decoder. Table 83. Bit Symbol Access Table 84. Bit 10.5.4.6 PreSet1D Register These bit settings must not be changed. ...
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... NXP Semiconductors 10.5.4.7 RxControl2 register Controls decoder behavior and defines the input source for the receiver. Table 87. Bit Symbol Access Table 88. Bit [1] I-clock and Q-clock are 90° phase-shifted from each other. 10.5.4.8 ClockQControl register Controls clock generation for the 90° phase-shifted Q-clock. ...
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... NXP Semiconductors 10.5.5 Page 4: RF Timing and channel redundancy 10.5.5.1 Page register Selects the page register; see 10.5.5.2 RxWait register Selects the time interval after transmission, before the receiver starts. Table 91. Bit Symbol Access Table 92. Bit 10.5.5.3 ChannelRedundancy register Selects kind and mode of checking the data integrity on the RF channel. ...
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... NXP Semiconductors Table 94. Bit Symbol 1 ParityOdd 0 ParityEn [1] With ISO/IEC 14443 A, this bit must be set to logic 1. 10.5.5.4 CRCPresetLSB register LSB of the preset value for the CRC register. Table 95. Bit Symbol Access Table 96. Bit 10.5.5.5 CRCPresetMSB register MSB of the preset value for the CRC register. ...
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... NXP Semiconductors Table 100. PreSet25 register bit descriptions Bit 10.5.5.7 MFOUTSelect register Selects the internal signal applied to pin MFOUT. Table 101. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation Bit Symbol Access Table 102. MFOUTSelect register bit descriptions ...
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... NXP Semiconductors 10.5.6 Page 5: FIFO, timer and IRQ pin configuration 10.5.6.1 Page register Selects the page register; see 10.5.6.2 FIFOLevel register Defines the levels for FIFO underflow and overflow warning. Table 105. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation ...
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... NXP Semiconductors 10.5.6.4 TimerControl register Selects start and stop conditions for the timer. Table 109. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation Bit Symbol Access Table 110. TimerControl register bit descriptions Bit Symbol 0000 3 TStopRxEnd 2 TStopRxBegin 1 TStartTxEnd ...
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... NXP Semiconductors 10.5.6.6 IRQPinConfig register Configures the output stage for pin IRQ. Table 113. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation Bit Symbol Access Table 114. IRQPinConfig register bit descriptions Bit 10.5.6.7 PreSet2E register Table 115. PreSet2E register (address: 2Eh) reset value: xxxx xxxxb, xxh bit allocation ...
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... NXP Semiconductors 10.5.8 Page 7: Test control 10.5.8.1 Page register Selects the page register; see 10.5.8.2 Reserved register 39h Table 118. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation Bit Symbol Access Remark: This register is reserved for future use. ...
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... NXP Semiconductors 10.5.8.4 Reserved register 3Bh Table 121. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation Bit Symbol Access Remark: This register is reserved for future use. 10.5.8.5 Reserved register 3Ch Table 122. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation ...
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... NXP Semiconductors 10.5.8.7 Reserved registers 3Eh, 3Fh Table 125. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation Bit Symbol Access Remark: This register is reserved for future use. 11. MFRC500 command set MFRC500 operation is determined by an internal state machine capable of performing a command set ...
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... NXP Semiconductors Table 126. MFRC500 commands overview Command Value Action [1] Transceive 1Eh transmits data from FIFO buffer to the card and automatically activates the receiver after transmission. The receiver waits until the time defined in the RxWait register has elapsed before starting. See Section 11 ...
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... NXP Semiconductors 11.1.1 Basic states 11.1.2 StartUp command 3Fh Table 127. StartUp command 3Fh Command StartUp Remark: This command can only be activated by a Power-On or Hard reset. The StartUp command runs the reset and initialization phases. It does not need or return, any data. It cannot be activated by the microprocessor but is automatically started after one of the following events: • ...
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... NXP Semiconductors 11.2 Commands for card communication The MFRC500 is a fully ISO/IEC 14443 A compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE reader ICs. A card communication and related communication protocols. 11.2.1 Transmit command 1Ah Table 129 ...
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... NXP Semiconductors 11.2.1.2 RF channel redundancy and framing Each ISO/IEC 14443 A frame transmitted consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. These different phases of the transmission sequence can be monitored using the PrimaryStatus register ModemState[2:0] bits; see Depending on the setting of the ChannelRedundancy register bit TxCRCEn, the CRC is calculated and appended to the data stream ...
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... NXP Semiconductors Fig 15. Timing for transmitting byte oriented frames As long as the internal signal accept further data is logic 1, data can be written to the FIFO buffer. The MFRC500 appends this data to the data stream transmitted using the RF interface. If the internal accept further data signal is logic 0, the transmission terminates. All data written to the FIFO buffer after the accept further data signal was set to logic 0 is not transmitted, however, it remains in the FIFO buffer ...
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... NXP Semiconductors Figure 16 status is checked. This leads to FIFO empty state being held LOW which keeps the accept further data active. The new byte written to the FIFO buffer is transmitted using the RF interface. Accept further data is only changed by the check FIFO empty function. This function verifies FIFO empty for one bit duration before the last expected bit transmission ...
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... NXP Semiconductors 11.2.2.2 RF channel redundancy and framing The decoder expects the SOF pattern at the beginning of each data stream. When the SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. Every completed byte is forwarded to the FIFO buffer EOF pattern is detected or the signal strength falls below the RxThreshold register MinLevel[3:0] bits setting, both the receiver and the decoder stop ...
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... NXP Semiconductors Table 132. Return values for bit-collision positions Collision in bit SOF Least Significant Bit (LSB) of the Least Significant Byte (LSByte) … Most Significant Bit (MSB) of the LSByte LSB of second byte … MSB of second byte LSB of third byte … Parity bits are not counted in the CollPos register because bit-collisions in parity bit occur after bit-collisions in the data bits ...
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... NXP Semiconductors Table 133. Communication error table Cause Received data did not start with the SOF pattern CRC block is not equal to the expected value Received data is shorter than the CRC block The parity bit is not equal to the expected value (i.e. a bit-collision, not parity) A bit-collision is detected 11 ...
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... NXP Semiconductors 11.2.5 Card communication state diagram Fig 17. Card communication state diagram MFRC500_33 Product data sheet PUBLIC Highly Integrated ISO/IEC 14443 A Reader IC COMMAND = TRANSMIT, RECEIVE OR TRANSCEIVE IDLE (000) FIFO not empty and command = command = Receive Transmit or Transceive TxSOF (001) SOF transmitted ...
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... NXP Semiconductors 11.3 EEPROM commands 11.3.1 WriteE2 command 01h Table 136. WriteE2 command 01h Command WriteE2 The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM start byte address. Any further bytes are interpreted as data bytes and are programmed into the EEPROM, starting from the given EEPROM start byte address ...
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... NXP Semiconductors 11.3.1.2 Timing diagram Figure 18 NWR write addr addr data byte 0 E2 LSB MSB WriteE2 command active EEPROM programming E2Ready TxIRq Fig 18. EEPROM programming timing diagram Assuming that the MFRC500 finds and reads byte 0 before the microprocessor is able to write byte which takes approximately 5 ...
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... NXP Semiconductors 11.3.2 ReadE2 command 03h Table 137. ReadE2 command 03h Command ReadE2 The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the EEPROM starting byte address. The next byte specifies the number of data bytes returned. When all three argument bytes are available in the FIFO buffer, the specified number of data bytes is copied from the EEPROM into the FIFO buffer, starting from the given EEPROM starting byte address ...
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... NXP Semiconductors 11.4.1.2 Relevant LoadConfig command error flags Valid EEPROM starting byte addresses are between 10h and 60h. Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the flag AccessErr = logic 1. Addresses above 1FFh are taken as modulo 200h; see EEPROM memory organization ...
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... NXP Semiconductors 11.5 Error handling during command execution If an error is detected during command execution, the PrimaryStatus register Err flag is set. The microprocessor can evaluate the status flags in the ErrorFlag register to get information about the cause of the error. Table 141. ErrorFlag register error flags overview ...
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... NXP Semiconductors The LoadKey command interprets the first twelve bytes it finds in the FIFO buffer as the key when stored in the correct key format as described in page 13. When the twelve argument bytes are available in the FIFO buffer they are checked and, if valid, are copied into the key buffer. ...
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... NXP Semiconductors 11.6.4.1 Authent2 command effects If the Authent2 command is successful, the authenticity of card and the MFRC500 are proved. This automatically sets the Crypto1On control bit. When bit Crypto1On = logic 1, all further card communication is encrypted using the Crypto1 security algorithm. If the Authent2 command fails, bit Crypto1On is cleared (Crypto1On = logic 0). ...
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... NXP Semiconductors 13.2 Current consumption Table 148. Current consumption Symbol Parameter I digital supply current DDD I analog supply current DDA I TVDD supply current DD(TVDD) 13.3 Pin characteristics 13.3.1 Input pin characteristics Pins D0 to D7, A0, and A1 have TTL input characteristics and behave as defined in Table 149 ...
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... NXP Semiconductors Pin RSTPD has Schmitt trigger CMOS characteristics. In addition internally filtered low-pass filter which causes a propagation delay on the reset signal. Table 151. RSTPD input pin characteristics Symbol Parameter The analog input pin RX has the input capacitance and input voltage range shown in Table 152 ...
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... NXP Semiconductors 13.3.3 Antenna driver output pin characteristics The source conductance of the antenna driver pins TX1 and TX2 for driving the HIGH-level can be configured using the CwConductance register’s GsCfgCW[5:0] bits, while their source conductance for driving the LOW-level is constant. The antenna driver default configuration output characteristics are specified in Table 154 ...
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... NXP Semiconductors ALE NCS NWR NRD Fig 19. Separate read/write strobe timing diagram Remark: The signal ALE is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care. The multiplexed address and data bus address lines (A0 to A2) must be connected as described in 13 ...
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... NXP Semiconductors Table 156. Common read/write strobe timing specification Symbol t AVDSL t RHAX t DSHDSL t WLDSL ALE NCS/NDS R/NW NRD Fig 20. Common read/write strobe timing diagram 13.4.3 EPP bus timing Table 157. Common read/write strobe timing specification for EPP Symbol t ASLASH t AVASH t ASHAV ...
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... NXP Semiconductors Table 157. Common read/write strobe timing specification for EPP Symbol t DSHDZ t DSLQV t DSHQX t DSHWX t DSLDSH t WLDSL t DSL-WAITH t DSH-WAITL Fig 21. Remark: cycle. The timings for the address write and data write cycle are different. In EPP mode, the address lines (A0 to A2) must be connected as described in ...
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... NXP Semiconductors 13.4.4 Clock frequency The clock input is pin OSCIN. Table 158. Clock frequency Symbol f clk δ clk t jit The clock applied to the MFRC500 acts as a time constant for the synchronous system’s encoder and decoder. The stability of the clock frequency is an important factor for ensuring proper performance ...
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... NXP Semiconductors 15. Application information 15.1 Typical application 15.1.1 Circuit diagram Figure 22 MFRC500: control lines MICROPROCESSOR Fig 22. Application example circuit diagram: directly matched antenna 15.1.2 Circuit description The matching circuit consists of an EMC low-pass filter (L0 and C0), matching circuitry (C1 and C2), a receiver circuit (R1, R2, C3 and C4) and the antenna itself. ...
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... NXP Semiconductors A multilayer board is recommended to implement a low-pass filter as shown in The low-pass filter consists of the components L0 and C0. The recommended values are given in Application notes MICORE reader IC family; Directly Matched Antenna Design Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Remark: To achieve best performance, all components must be at least equal in quality to those recommended ...
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... NXP Semiconductors 15.1.2.4 Antenna coil The precise calculation of the antenna coil’s inductance is not practicable but the inductance can be estimated using that is either circular or rectangular • length of one turn of the conductor loop 1 • diameter of the wire or width of the PCB conductor, respectively 1 • ...
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... NXP Semiconductors 15.2.1 Measurements using the serial signal switch Using the serial signal switch on pin MFOUT, data is observed that is sent to the card or received from the card. Table 160. Signal routed to pin MFOUT SignalToMFOUT 15.2.1.1 TX control Figure 23 The signal is measured on pin MFOUT using the serial signal switch to control the data sent to the card ...
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... NXP Semiconductors (1) MFOUTSelect[2: serial data stream per division. (2) MFOUTSelect[2: serial data stream per division. (3) RFOut per division. Fig 23. TX control signals 15.2.1.2 RX control Figure 24 beginning of a card’s answer to a request signal. The RF signal shows the RF voltage measured directly on the antenna so that the card’s load modulation is visible ...
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... NXP Semiconductors (1) RFOut per division. (2) MFOUTSelect[2: Manchester with subcarrier per division. (3) MFOUTSelect[2: Manchester per division. Fig 24. RX control signals 15.2.2 Analog test signals The analog test signals can be routed to pin AUX by selecting them using the TestAnaSelect register TestAnaOutSel[4:0] bits. Table 161. Analog test signal selection ...
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... NXP Semiconductors Table 161. Analog test signal selection Value 15.2.3 Digital test signals Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1. A digital test signal is selected using the TestDigiSelect register TestDigiSignalSel[6:0] bits. The signals selected by the TestDigiSignalSel[6:0] bits are shown in Table 162 ...
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... NXP Semiconductors RX reference VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data s_valid Fig 25. ISO/IEC 14443 A receiving path Q-clock MFRC500_33 Product data sheet PUBLIC Highly Integrated ISO/IEC 14443 A Reader IC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 15 March 2010 048033 MFRC500 50 μ ...
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... NXP Semiconductors 16. Package outline SO32: plastic small outline package; 32 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 17. Abbreviations Table 163. Abbreviations and acronyms Acronym ASK CMOS CRC EOF EPP ETU FIFO HBM LSB MM MSB NRZ POR PCD PICC SOF SPI 18. References [1] Application note — MICORE reader IC family; Directly Matched Antenna Design. [2] Application note — MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas. ...
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... This version supersedes all previous revisions. • The symbols for electrical characteristics and their parameters have been updated to meet the NXP Semiconductors’ guidelines • A number of inconsistencies in pin, register and bit names have been eliminated from the data sheet • ...
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... NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 22. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 4. Supported microprocessor and EPP interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 5. Connection scheme for detecting the parallel interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 6. EEPROM memory organization diagram . . . . .10 Table 7. Product information field byte allocation . . . . . 11 Table 8. ...
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... NXP Semiconductors reset value: 0011 1111b, 3Fh bit allocation . . .53 Table 68. PreSet13 register bit descriptions . . . . . . . . . .53 Table 69. PreSet14 register (address: 14h) reset value: 0001 1001b, 19h bit allocation . . .53 Table 70. PreSet14 register bit descriptions . . . . . . . . . .53 Table 71. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation . . .54 Table 72 ...
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... NXP Semiconductors Table 135. Meaning of ModemState . . . . . . . . . . . . . . . . .75 Table 136. WriteE2 command 01h . . . . . . . . . . . . . . . . . .77 Table 137. ReadE2 command 03h . . . . . . . . . . . . . . . . . .79 Table 138. LoadConfig command 07h . . . . . . . . . . . . . . .79 Table 139. CalcCRC command 12h . . . . . . . . . . . . . . . . .80 Table 140. CRC coprocessor parameters . . . . . . . . . . . .80 Table 141. ErrorFlag register error flags overview . . . . . .81 Table 142. LoadKeyE2 command 0Bh . . . . . . . . . . . . . . .81 Table 143 ...
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... NXP Semiconductors 23. Figures Fig 1. MFRC500 block diagram . . . . . . . . . . . . . . . . . . . .4 Fig 2. MFRC500 pin configuration . . . . . . . . . . . . . . . . . .5 Fig 3. Connection to microprocessor: separate read and write strobes . . . . . . . . . . . . . . . . . . . . . .8 Fig 4. Connection to microprocessor: common read and write strobes . . . . . . . . . . . . . . . . . . . . . .9 Fig 5. Connection to microprocessor: EPP common read/write strobes and handshake Fig 6. Key storage format . . . . . . . . . . . . . . . . . . . . . . .14 Fig 7. ...
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... NXP Semiconductors 24. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 6 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 8.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Functional description . . . . . . . . . . . . . . . . . . . 7 9.1 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.1 Overview of supported microprocessor interfaces ...
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... NXP Semiconductors 10 MFRC500 registers . . . . . . . . . . . . . . . . . . . . . 37 10.1 Register addressing modes . . . . . . . . . . . . . . 37 10.1.1 Page registers . . . . . . . . . . . . . . . . . . . . . . . . 37 10.1.2 Dedicated address bus . . . . . . . . . . . . . . . . . . 37 10.1.3 Multiplexed address bus . . . . . . . . . . . . . . . . . 37 10.2 Register bit behavior 10.3 Register overview . . . . . . . . . . . . . . . . . . . . . . 39 10.4 MFRC500 register flags overview 10.5 Register descriptions . . . . . . . . . . . . . . . . . . . 43 10.5.1 Page 0: Command and status . . . . . . . . . . . . 43 10.5.1.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 ...
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... NXP Semiconductors 11.3.1.2 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 78 11.3.1.3 WriteE2 command error flags . . . . . . . . . . . . . 78 11.3.2 ReadE2 command 03h . . . . . . . . . . . . . . . . . . 79 11.3.2.1 ReadE2 command error flags 11.4 Diverse commands . . . . . . . . . . . . . . . . . . . . . 79 11.4.1 LoadConfig command 07h . . . . . . . . . . . . . . . 79 11.4.1.1 Register assignment . . . . . . . . . . . . . . . . . . . . 79 11.4.1.2 Relevant LoadConfig command error flags . . 80 11.4.2 CalcCRC command 12h . . . . . . . . . . . . . . . . . 80 11.4.2.1 CRC coprocessor settings . . . . . . . . . . . . . . . 80 11 ...