MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 16

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
9.3.4 FIFO buffer registers and flags
9.4.1 Interrupt sources overview
9.4 Interrupt request system
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by
Table 14
Table 14.
The MFRC500 indicates interrupt events by setting the PrimaryStatus register bit IRq (see
Section 10.5.1.4 “PrimaryStatus register” on page
on pin IRQ can be used to interrupt the microprocessor using its interrupt handling
capabilities ensuring efficient microprocessor software.
Table 15
interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows:
The RxIRq flag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq flag bit is set when a command finishes and the content of the Command
register changes to Idle.
HiAlert
LoAlert
Flags
FIFOLength[6:0]
FIFOOvfl
FlushFIFO
HiAlert
HiAlertIEn
HiAlertIRq
LoAlert
LoAlertIEn
LoAlertIRq
WaterLevel[5:0]
•
•
•
the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern
the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady = logic 1
when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit
E2Ready = logic 1
=
=
shows the related FIFO buffer flags in alphabetic order.
shows the integrated interrupt flags, related source and setting condition. The
Associated FIFO buffer registers and flags
(
FIFOLength
64 FIFOLength
–
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 15 March 2010
ErrorFlag
Register name
FIFOLength
Control
PrimaryStatus
InterruptEn
InterruptRq
PrimaryStatus
InterruptEn
InterruptRq
FIFOLevel
≤
WaterLevel
)
048033
≤
WaterLevel
Highly Integrated ISO/IEC 14443 A Reader IC
Bit
6 to 0
4
0
1
1
1
0
0
0
5 to 0
45) and activating pin IRQ. The signal
Equation
Register address
04h
0Ah
09h
03h
06h
07h
03h
06h
07h
29h
MFRC500
© NXP B.V. 2010. All rights reserved.
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