CLRC63201T/0FE,112 NXP Semiconductors, CLRC63201T/0FE,112 Datasheet - Page 19

IC I.CODE HS READER 32-SOIC

CLRC63201T/0FE,112

Manufacturer Part Number
CLRC63201T/0FE,112
Description
IC I.CODE HS READER 32-SOIC
Manufacturer
NXP Semiconductors
Series
I-Coder
Datasheets

Specifications of CLRC63201T/0FE,112

Rf Type
Read Only
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B, ISO15693, ISO18000-3
Package / Case
32-SOIC (0.300", 7.50mm Width)
Product
RFID Readers
Operating Temperature Range
- 25 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2199-5
935269690112
CLRC632
CLRC63201TD

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
CLRC63201T/0FE,112
Manufacturer:
IR
Quantity:
3 400
Part Number:
CLRC63201T/0FE,112
Manufacturer:
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Quantity:
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NXP Semiconductors
CLRC632_35
Product data sheet
PUBLIC
9.3.1.1 Access rules
9.3.1 Accessing the FIFO buffer
9.3.2 Controlling the FIFO buffer
9.3 FIFO buffer
An 8
It buffers both the input and output data streams between the microprocessor and the
internal circuitry of the CLRC632. This makes it possible to manage data streams up to 64
bytes long without needing to take timing constraints into account.
The FIFO buffer input and output data bus is connected to the FIFOData register. Writing
to this register stores one byte in the FIFO buffer and increments the FIFO buffer write
pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO
buffer read pointer and increments the FIFO buffer read pointer. The distance between the
write and read pointer can be obtained by reading the FIFOLength register.
When the microprocessor starts a command, the CLRC632 can still access the FIFO
buffer while the command is running. Only one FIFO buffer has been implemented which
is used for input and output. Therefore, the microprocessor must ensure that there are no
inadvertent FIFO buffer accesses.
during command processing.
Table 18.
In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
Active
command
StartUp
Idle
Transmit
Receive
Transceive
WriteE2
ReadE2
LoadKeyE2
LoadKey
Authent1
Authent2
LoadConfig
CalcCRC
64 bit FIFO buffer is used in the CLRC632 to act as a parallel-to-parallel converter.
FIFO buffer access
FIFO buffer
-
-
yes
-
yes
yes
yes
yes
yes
yes
-
yes
yes
p Write
Rev. 3.5 — 10 November 2009
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
-
-
-
yes
yes
-
yes
-
-
-
-
-
-
p Read
073935
Table 18
Remark
the microprocessor has to know the state of the
command (transmitting or receiving)
the microprocessor has to prepare the arguments,
afterwards only reading is allowed
gives an overview of FIFO buffer access
CLRC632
© NXP B.V. 2009. All rights reserved.
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