MFRC52201HN1,151 NXP Semiconductors, MFRC52201HN1,151 Datasheet - Page 16

• Manufacturer Part Number: MFRC52201HN1,151
• Description: IC READER 13.56MHZ 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of MFRC52201HN1,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280547151

NXP Semiconductors
112132
Product data sheet
9.2.1.4 DivIEnReg
9.2.1.5 CommIRqReg
Control bits to enable and disable the passing of interrupt requests.
Table 13:
Table 14:
Contains Interrupt Request bits.
Table 15:
Table 16:
All bits in the register CommIRqReg shall be cleared by software.
Bit
7
6 to 5
4
3
2
1 to 0
Bit
7
6
5
4
3
Symbol IRQPushPull
Access
Symbol
Access
Rights
Rights
Bit
Bit
Symbol
Set1
TxIRq
RxIRq
IdleIRq
HiAlertIRq
Symbol
IRQPushPull
-
MfinActIEn
-
CRCIEn
-
Description of DivIEnReg bits
Description of CommIRqReg bits
DivIEnReg register (address 03h); reset value: 00h
CommIRqReg register (address 04h); reset value: 14h
Set1
w
7
r/w
7
Description
Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg
are set.
Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg
are cleared.
Set to logic 1 immediately after the last bit of the transmitted data was sent out.
Set to logic 1 when the receiver detects the end of a valid data stream.
If the bit RxNoErr in register RxModeReg is set to logic 1, Bit RxIRq is only set
to logic 1 when data bytes are available in the FIFO.
Set to logic 1, when a command terminates by itself e.g. when the
CommandReg changes its value from any command to the Idle Command.
If an unknown command is started, the CommandReg changes its content to
the idle state and the bit IdleIRq is set. Starting the Idle Command by the
μ-Controller does not set bit IdleIRq.
Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to
HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit
Set1.
TxIRq
dy
6
Rev. 3.2 — 22 May 2007
Description
Set to logic 1, the pin IRQ works as standard CMOS output pad.
Set to logic 0, the pin IRQ works as open drain output pad.
Reserved for future use.
Allows the MFIN active interrupt request to be propagated to pin IRQ.
Reserved for future use.
Allows the CRC interrupt request (indicated by bit CRCIRq) to be
propagated to pin IRQ.
Reserved for future use.
6
RFU
RxIRq
-
dy
5
5
IdleIRq
dy
MfinActIEn
4
r/w
4
HiAlertIRq LoAlertIRq
dy
3
RFU
3
-
CRCIEn
dy
2
r/w
Contactless Reader IC
2
MFRC522
© NXP B.V. 2007. All rights reserved.
ErrIRq
dy
1
1
RFU
-
TimerIRq
16 of 109
dy
0
0