MFRC52201HN1,151 NXP Semiconductors, MFRC52201HN1,151 Datasheet - Page 19

• Manufacturer Part Number: MFRC52201HN1,151
• Description: IC READER 13.56MHZ 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of MFRC52201HN1,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280547151

NXP Semiconductors
112132
Product data sheet
9.2.1.8 Status1Reg
Contains status bits of the CRC, Interrupt and FIFO buffer.
Table 21:
Table 22:
Bit
7
6
5
4
3
2
1
0
Symbol
Access
Rights
Bit
Symbol
-
CRCOk
CRCReady
IRq
TRunning
-
HiAlert
LoAlert
Status1Reg register (address 07h); reset value: 21h
Description of Status1Reg bits
RFU
7
-
CRCOk CRCReady
6
r
Rev. 3.2 — 22 May 2007
Description
Reserved for future use.
Set to logic 1, if the CRC result is zero. For data transmission and
reception the bit CRCOk is undefined (use CRCErr in register
ErrorReg). CRCOk indicates the status of the CRC co-processor,
during calculation the value changes to logic 0, when the calculation is
done correctly, the value changes to logic 1.
Set to logic 1, when the CRC calculation has finished. This bit is only
valid for the CRC co-processor calculation using the command
CalcCRC.
This bit shows, if any interrupt source requests attention (with respect
to the setting of the interrupt enable bits, see register CommIEnReg
and DivIEnReg).
Set to logic 1, if the MFRC522’s timer unit is running, e.g. the timer will
decrement the TCounterValReg with the next timer clock.
Remark: In the gated mode the bit TRunning is set to logic 1, when
Reserved for future use.
Set to logic 1, when the number of bytes stored in the FIFO buffer
fulfils the following equation:
Example:
Set to logic 1, when the number of bytes stored in the FIFO buffer
fulfils the following equation:
Example:
HiAlert
LoAlert
FIFOLength = 60, WaterLevel = 4 → HiAlert = 1
FIFOLength = 59, WaterLevel = 4 → HiAlert = 0
FIFOLength = 4, WaterLevel = 4 → LoAlert = 1
FIFOLength = 5, WaterLevel = 4 → LoAlert = 0
5
r
the timer is enabled by the register bits. This bit is not
influenced by the gated signal.
=
=
(
FIFOLength WaterLevel
64 FIFOLength
–
IRq
4
r
≤
TRunning
)
≤
3
r
WaterLevel
RFU
2
-
Contactless Reader IC
MFRC522
© NXP B.V. 2007. All rights reserved.
HiAlert
1
r
LoAlert
19 of 109
0
r