ELLXT971ABC.A4-870477 Cortina Systems Inc, ELLXT971ABC.A4-870477 Datasheet - Page 27

• Manufacturer Part Number: ELLXT971ABC.A4-870477
• Description: TXRX FAST ETH COMM TEMP 64-PBGA
• Manufacturer: Cortina Systems Inc

Specifications of ELLXT971ABC.A4-870477

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1003

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
5.2.2
5.2.3
5.2.3.1
Cortina Systems
The occurrence of a Far End Fault causes all transmission of data from the Reconciliation
Sublayer to stop and the Far End fault code to begin. The Far End Fault code consists of
84 ones followed by a single zero. (This pattern must be repeated three times.)
If the LXT971A PHY detects a signal fault condition, it can transmit the Far-End Fault
Indication (FEFI) over the fiber link. The FEFI consists of 84 consecutive ones followed by
a single zero. This pattern must be repeated at least three times. The LXT971A PHY
transmits the far-end fault code a minimum of three times if all the following conditions are
true:
MII Data Interface
The LXT971A PHY supports a standard Media Independent Interface (MII). The MII
consists of a data interface and a management interface. The MII Data Interface passes
data between the LXT971A PHY and a Media Access Controller (MAC). Separate parallel
buses are provided for transmit and receive. This interface operates at either 10 Mbps or
100 Mbps. The speed is set automatically, once the operating conditions of the network
link have been determined. For details, see
Increased MII Drive Strength. A higher Media Independent Interface (MII) drive strength
may be desired in some designs to drive signals over longer PCB trace lengths, or over
high-capacitive loads, through multiple vias, or through a connector. The MII drive
strength in the LXT971A PHY can be increased by setting register bit 26.11 through
software control. Setting register bit 26.11 = 1 through the MDC/MDIO interface sets the
MII pins (RXD[3:0], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a higher drive
strength.
Configuration Management Interface
The LXT971A PHY provides both an MDIO interface and a reduced hardware control
interface for device configuration and management.
MDIO Management Interface
MDIO management interface topics include the following:
®
• When register bit 16.2 = 0, the LXT971A PHY does not transmit far end fault code. It
• When register bit 16.2 = 1, transmission of the far end fault code is enabled. The
• Fiber mode is selected.
• Fault Code transmission is enabled (register bit 16.2 = 1).
• Either Signal Detect indicates no signal, or the receive PLL cannot lock.
• Loopback is not enabled.
•
•
•
LXT971A Single-Port 10/100 Mbps PHY Transceiver
continues to transmit idle code and may or may not drop link depending on the setting
for register bit 16.14.
LXT971A PHY transmits far end fault code if fault conditions are detected by the SD/
TP_L pin.
Section 5.2.3.1.1, MDIO Addressing
Section 5.2.3.1.2, MDIO Frame Structure
Section 5.2.3.1.3, MII Interrupts
Section 5.6, MII Operation, on page
5.2 Network Media / Protocol
36.
Support
Page 27