ELLXT971ABC.A4-870477 Cortina Systems Inc, ELLXT971ABC.A4-870477 Datasheet - Page 82

• Manufacturer Part Number: ELLXT971ABC.A4-870477
• Description: TXRX FAST ETH COMM TEMP 64-PBGA
• Manufacturer: Cortina Systems Inc

Specifications of ELLXT971ABC.A4-870477

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1003

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Table 50
Cortina Systems
Auto-Negotiation Advertisement Register - Address 4, Hex 4
®
1. R/W = Read/Write
2. Default setting is determined by pin 33/H8 at reset.
3. Some bits have their default values determined at reset by hardware configuration pins. For default details
4.4:0
4.15
4.14
4.13
4.12
4.11
4.10
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Bit
4.9
4.8
4.7
4.6
4.5
RO = Read Only
for these bits, see
Next Page
Reserved
Remote Fault
Reserved
Asymmetric Pause
Pause
100BASE-T4
100BASE-TX
full-duplex
(For LXT971A PHY)
100BASE-TX
(For LXT971A PHY)
10BASE-T
full-duplex
(ForLXT971A PHY)
10BASE-T
Selector Field,
S<4:0>
Name
Section 5.4.4, Hardware Configuration Settings
0 = Port has no ability to send multiple pages.
1 = Port has ability to send multiple pages.
Ignore when read.
0 = No remote fault.
1 = Remote fault.
Write as ‘0’. Ignore on Read.
Pause operation defined in IEEE 802.3 Standard,
Clause 40 and 27
0 = Pause operation disabled.
1 = Pause operation enabled for full-duplex link.
0 = 100BASE-T4 capability is not available.
1 = 100BASE-T4 capability is available.
Note:
0 = Port is not 100BASE-TX full-duplex capable.
1 = Port is 100BASE-TX full-duplex capable.
0 = Port is not 100BASE-TX capable.
1 = Port is 100BASE-TX capable.
0 = Port is not 10BASE-T full-duplex capable.
1 = Port is 10BASE-T full-duplex capable.
0 = Port is not 10BASE-T capable.
1 = Port is 10BASE-T capable.
00001 =IEEE 802.3.
00010 =IEEE 802.9 ISLAN-16T.
00000 =Reserved for future auto-negotiation
11111 = Reserved for future auto-negotiation
Note:
development.
development.
The LXT971A PHY does not support
100BASE-T4 but allows this bit to be set
to advertise in the auto-negotiation
sequence for 100BASE-T4 operation. An
external 100BASE-T4 PHY can be
switched in if this capability is desired.
Unspecified or reserved combinations
must not be transmitted.
Description
.
8.0 Register Definitions - IEEE
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
1
Base Registers
Default
Note 2
Note 3
Note 3
Note 3
Note 3
00001
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0
0
0
0
0
0