LFE3-150EA-7FN1156CTW Lattice, LFE3-150EA-7FN1156CTW Datasheet - Page 119
LFE3-150EA-7FN1156CTW
Manufacturer Part Number
LFE3-150EA-7FN1156CTW
Description
FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -7 Speed
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672CTW.pdf
(130 pages)
Specifications of LFE3-150EA-7FN1156CTW
Number Of Programmable I/os
133 to 586
Data Ram Size
6.85 Mbits
Delay Time
37 ns
Supply Voltage (max)
1.26 V
Supply Current
18 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-1156
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-150EA-7FN1156CTW
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 119 of 130
- Download datasheet (3Mb)
Lattice Semiconductor
Logic Signal Connections
Package pinout information can be found under “Data Sheets” on the LatticeECP3 product pages on the Lattice
website at
ate pinout information from within Design Planner, select View -> Package View. Then select Select File ->
Export and choose a type of output file. See Design Planner help for more information.
Thermal Management
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal
characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.
Designers must complete a thermal analysis of their specific design to ensure that the device and package do not
exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package
specific thermal values.
For Further Information
For further information regarding Thermal Management, refer to the following:
•
• TN1181,
• Power Calculator tool included with the Lattice ispLEVER design tool, or as a standalone download from
Thermal Management
www.latticesemi.com/software
www.latticesemi.com/products/fpga/ecp3
Power Consumption and Management for LatticeECP3 Devices
document
and in the Lattice ispLEVER Design Planner software. To cre-
4-10
LatticeECP3 Family Data Sheet
Pinout Information
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