LFE3-150EA-7FN1156CTW Lattice, LFE3-150EA-7FN1156CTW Datasheet - Page 70

• Manufacturer Part Number: LFE3-150EA-7FN1156CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN1156CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-1156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP3 External Switching Characteristics (Continued)
Lattice Semiconductor
f
Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_RX.DQS.Centered) Using DQS
Pin for Clock Input
Left, Right and Top for Data and Clock
t
t
f
Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Aligned at Pin (GDDRX1_RX.DQS.Aligned) Using DQS Pin
for Clock Input
Left and Right Sides
t
t
f
Top Side
t
t
f
Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK
Pin for Clock Input
Left and Right Sides
t
t
f
Generic DDRX2 Inputs with Clock in the Center of Data Window, Without DLL
t
t
f
Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX2_RX.ECLK.Aligned)
Left and Right Side Using DLLCLKIN Pin for Clock Input
t
t
f
Top Side Using PCLK Pin for Clock Input
t
t
f
Generic DDRX2 Inputs with Clock and Data Edges Aligned, with DLLDEL
t
MAX_GDDR
SUGDDR
HGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
SUGDDR
HGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
Parameter
DDRX1 Clock Frequency
Data Valid After CLK
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup Before CLK (Left and
Right Sides)
Data Hold After CLK (Left and Right
Sides)
DDRX1 Clock Frequency (Left and
Right Sides)
Data Setup Before CLK (Top Side)
Data Hold After CLK (Top Side)
DDRX1 Clock Frequency (Top Side)
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDR/DDRX2 Clock Frequency
Data Setup Before CLK (Left and
Right Side)
Data Hold After CLK (Left and Right
Side)
DDRX1 Clock Frequency (Left and
Right Side)
Data Setup Before CLK (Top Side)
Data Hold After CLK (Top Side)
DDRX1 Clock Frequency (Top Side)
Data Valid After CLK
Over Recommended Commercial Operating Conditions
Description
8
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
3-18
Device
Min.
260
260
—
—
—
—
—
—
—
—
—
—
—
—
—
3
DC and Switching Characteristics
(GDDRX2_RX.ECLK.Aligned)
-8
LatticeECP3 Family Data Sheet
3
0.235
Max.
(GDDRX2_RX.ECLK.Centered)
250
500
—
—
—
—
—
—
—
—
—
—
Min.
312
312
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
0.235
Max.
250
420
1, 2
—
—
—
—
—
—
—
—
—
—
Min.
352
352
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
0.235
Max.
250
375
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ps
ps
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI