LFE3-150EA-7FN1156CTW Lattice, LFE3-150EA-7FN1156CTW Datasheet - Page 73

• Manufacturer Part Number: LFE3-150EA-7FN1156CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN1156CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-1156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP3 External Switching Characteristics (Continued)
Lattice Semiconductor
f
DDR3 (Using PLL for SCLK) I/O Pin Parameters
t
t
t
t
f
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the ispLEVER software.
2. General I/O timing numbers based on LVCMOS 2.5, 12mA, 0pf load.
3. Generic DDR timing numbers based on LVDS I/O.
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18.
5. DDR3 timing numbers based on SSTL15.
6. Uses LVDS I/O standard.
7. The current version of software does not support per bank skew numbers; this will be supported in a future release.
8. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
MAX_DDR2
DVADQ
DVEDQ
DQVBS
DQVAS
MAX_DDR3
Parameter
DDR2 Clock Frequency
Data Valid After DQS (DDR Read)
Data Hold After DQS (DDR Read)
Data Valid Before DQS
Data Valid After DQS
DDR3 clock frequency
Over Recommended Commercial Operating Conditions
Description
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
3-21
Device
Min.
0.64
0.25
0.25
133
266
—
DC and Switching Characteristics
-8
LatticeECP3 Family Data Sheet
0.225
Max.
266
400
—
—
—
Min.
0.64
0.25
0.25
133
266
—
-7
0.225
Max.
200
333
1, 2
—
—
—
Min.
0.64
0.25
0.25
133
266
—
-6
0.225
Max.
166
300
—
—
—
Units
MHz
MHz
UI
UI
UI
UI