LFE3-150EA-7FN1156CTW Lattice, LFE3-150EA-7FN1156CTW Datasheet - Page 21

• Manufacturer Part Number: LFE3-150EA-7FN1156CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN1156CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-1156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-20. Sources of Edge Clock (Left and Right Edges)
Figure 2-21. Sources of Edge Clock (Top Edge)
The edge clocks have low injection delay and low skew. They are used to clock the I/O registers and thus are ideal
for creating I/O interfaces with a single clock signal and a wide data bus. They are also used for DDR Memory or
Generic DDR interfaces.
from DLL Slave Delay
from DLL Slave Delay
Top Right PLL_CLKOS
Top Right PLL_CLKOP
Top Left PLL_CLKOS
DLL Output CLKOP
DLL Output CLKOS
PLL Output CLKOP
PLL Output CLKOS
Top left PLL_CLKOP
Right DLL_CLKOS
Right DLL_CLKOP
Left DLL_CLKOP
Left DLL_CLKOS
(Right DLL_DEL)
PLL Input Pad
PLL Input Pad
(Left DLL_DEL)
CLKINDEL
CLKINDEL
Input Pad
Input Pad
CLKINDEL
CLKINDEL
Input Pad
Input Pad
Routing
Routing
Routing
Routing
2-18
6:1
6:1
7:1
7:1
Left and Right
Left and Right
Edge Clocks
Edge Clocks
ECLK1
ECLK2
ECLK1
ECLK2
LatticeECP3 Family Data Sheet
Architecture