ISL6334AIRZR5368 Intersil, ISL6334AIRZR5368 Datasheet - Page 20

• Manufacturer Part Number: ISL6334AIRZR5368
• Description: IC CTRLR PWM 4PHASE BUCK 40QFN
• Manufacturer: Intersil

Specifications of ISL6334AIRZR5368

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 V ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 V ~ 1.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Assuming the microprocessor controls the VID change at
1-bit every t
of R
During dynamic VID transition and VID steps up, the
overcurrent trip point increases by 140% to avoid falsely
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If the dynamic VID occurs
at PSI# asserted, the system should exit PSI# and complete
the transition, and then resume PSI# operation 50µs after
the transition.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a high-
impedance state to assure the drivers remain off. The following
input conditions must be met before the ISL6334AR5368 is
released from shutdown mode.
When all conditions previously mentioned are satisfied,
ISL6334AR5368 begins the soft-start and ramps the output
voltage to 1.1V first. After remaining at 1.1V for some time,
ISL6334AR5368 reads the VID code at VID input pins. If the
VID code is valid, ISL6334AR5368 will regulate the output to
the final VID setting. If the VID code is OFF code,
ISL6334AR5368 will shut down, and cycling VCC, EN_PWR
or EN_VTT is needed to restart.
C
1. The bias voltage applied at VCC must reach the internal
2. The ISL6334AR5368 features an enable input
3. The voltage on EN_VTT must be higher than 0.875V to
REF
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6334AR5368 are guaranteed. Hysteresis
between the rising and falling thresholds assure that once
enabled, ISL6334AR5368 will not inadvertently turn off
unless the bias voltage drops substantially (see
“Electrical Specifications” table beginning on page 8).
(EN_PWR) for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6334AR5368 in shutdown until
the voltage at EN_PWR rises above 0.875V. The enable
comparator has about 130mV of hysteresis to prevent
bounce. It is important that the driver reach their POR
level before the ISL6334AR5368 becomes enabled. The
schematic in Figure 8 demonstrates sequencing the
ISL6334AR5368 with the ISL66xx family of Intersil
MOSFET drivers, which require 12V bias.
enable the controller. This pin is typically connected to the
output of VTT VR.
REF
R
REF
and C
VID
=
REF
, the relationship between the time constant
t
VID
network and t
20
VID
is given by Equation 13.
(EQ. 13)
ISL6334AR5368
Soft-Start
ISL6334AR5368 based VR has 4 periods during soft-start, as
shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, the controller will have a fixed
delay period t
soft-start ramp until the output voltage reaches 1.1V Vboot
voltage. Then, the controller will regulate the VR voltage at 1.1V
for another fixed period t
ISL6334AR5368 reads the VID signals. If the VID code is valid,
ISL6334AR5368 will initiate the second soft-start ramp until the
voltage reaches the VID voltage minus offset voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 14.
t
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore, the minimum t
During t
DAC voltage change at 6.25mV per step. The time for each
step is determined by the frequency of the soft-start oscillator,
which is defined by the resistor R
second soft-start ramp time t
based on Equations 15 and 16:
t
t
D1
SS
D2
FIGURE 8. POWER SEQUENCING USING THRESHOLD-
is a fixed delay with the typical value as 1.36ms. t
=
=
1.1xR
----------------------- - μs
t
6.25x25
FAULT LOGIC
D1
SOFT-START
CIRCUIT
D2
POR
+
and t
AND
t
SS
D2
D1
SENSITIVE ENABLE (EN) FUNCTION
(
+
. After this delay period, the VR will begin first
D4
INTERNAL CIRCUIT
t
D3
)
, ISL6334AR5368 digitally controls the
ISL6334AR5368
+
COMPARATOR
t
D4
D3
ENABLE
D3
. At the end of t
D2
is about 86µs.
+
-
0.875V
+
-
0.875V
and t
SS
from SS pin to GND. The
D4
can be calculated
VCC
EN_VTT
EN_PWR
D3
EXTERNAL CIRCUIT
period,
100kΩ
9.1kΩ
September 7, 2010
+12V
(EQ. 14)
(EQ. 15)
D3
FN6839.2
is