ISL6334AIRZR5368 Intersil, ISL6334AIRZR5368 Datasheet - Page 21

• Manufacturer Part Number: ISL6334AIRZR5368
• Description: IC CTRLR PWM 4PHASE BUCK 40QFN
• Manufacturer: Intersil

Specifications of ISL6334AIRZR5368

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 V ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 V ~ 1.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For example, when VID is set to 1.5V and the R
100kΩ, the first soft-start ramp time t
second soft-start ramp time t
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t
typical value for t
released, the controller disregards the PSI# input and
always operates in normal CCM PWM mode.
Current Sense Output
The current flowing out of the IMON pin is equal to the
sensed average current inside ISL6334AR5368. In typical
applications, a resistor is placed from the IMON pin to GND
to generate a voltage, which is proportional to the load
current and the resistor value, as shown in Equation 17:
where V
resistor between the IMON pin and GND, I
output current of the converter, R
connected to the ISEN+ pin, N is the active channel number,
and R
either the DCR of the inductor or R
sensing method.
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is less than 1.11V
under the maximum load current. If the IMON pin voltage is
higher than 1.11V, overcurrent shutdown will be triggered, as
described in “Overcurrent Protection” on page 22.
A small capacitor can be placed between the IMON pin and
GND to reduce the noise impact. If this pin is not used, tie it
to GND.
V
t
D4
IOUT
=
X
(
------------------------------------------------ μs
=
V
is the DC resistance of the current sense element,
IMON
VID
------------------ -
R
6.25x25
IOUT
FIGURE 9. SOFT-START WAVEFORMS
N
–
1.1
is the voltage at the IMON pin, R
VOUT, 500mV/DIV
D5
----------------- - I
R
)xR
ISEN
R
t
D1
X
is 85µs. Before the VR_RDY is
SS
EN_VTT
VR_RDY
(
LOAD
)
t
D4
D2
500µs/DIV
21
will be 256µs.
t
ISEN
D3
SENSE
D2
t
D4
is the sense resistor
will be 704µs and the
t
depending on the
LOAD
D5
IMON
SS
D5
is the total
. The
is set at
(EQ. 16)
(EQ. 17)
is the
ISL6334AR5368
Fault Monitoring and Protection
The ISL6334AR5368 actively monitors output voltage and
current to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to a microprocessor
load. One common power-good indicator is provided for linking
to external system monitors. The schematic in Figure 10
outlines the interaction between the fault monitors and the
VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output which
indicates that the soft-start period has completed and the
output voltage is within the regulated range. VR_RDY is
pulled low during shutdown and releases high after a
successful soft-start and a fixed delay t
pulled low when an undervoltage or overvoltage condition is
detected, or the controller is disabled by a reset from
EN_PWR, EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the
ISL6334AR5368 overvoltage protection (OVP) circuit will be
active after its POR. The OVP thresholds are different under
different operation conditions. When VR is not enabled and
during the soft-start intervals t
threshold is 1.273V. Once the controller detects valid VID
input, the OVP trip point will be changed to DAC plus
175mV.
Two actions are taken by ISL6334AR5368 to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns). This causes
the Intersil drivers to turn on the lower MOSFETs and pull
the output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC plus 75mV,
PWM signals enter a high-impedance state. The Intersil
drivers respond to the high-impedance input by turning off
both upper and lower MOSFETs. If the overvoltage condition
reoccurs, ISL6334AR5368 will again command the lower
MOSFETs to turn on. ISL6334AR5368 will continue to
protect the load in this fashion as long as the overvoltage
condition occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until ISL6334AR5368 is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the
POR-falling threshold will reset the controller. Cycling the
VID codes will not reset the controller.
D1
, t
D2
and t
D5
. VR_RDY will be
D3
, the OVP
September 7, 2010
FN6839.2