ZL6100EVAL1Z Intersil, ZL6100EVAL1Z Datasheet - Page 22

no-image

ZL6100EVAL1Z

Manufacturer Part Number
ZL6100EVAL1Z
Description
EVAL BOARD USB ZL6100
Manufacturer
Intersil
Datasheets

Specifications of ZL6100EVAL1Z

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ZL6100EVAL1Z
Manufacturer:
Intersil
Quantity:
4
Loop Compensation
The ZL6100 operates as a voltage-mode synchronous buck
controller with a fixed frequency PWM scheme. Although the
ZL6100 uses a digital control loop, it operates much like a
traditional analog PWM controller. Figure 16 is a simplified
block diagram of the ZL6100 control loop, which differs from
an analog control loop only by the constants in the PWM and
compensation blocks. As in the analog controller case, the
compensation block compares the output voltage to the
desired voltage reference and compensation zeroes are
added to keep the loop stable. The resulting integrated error
signal is used to drive the PWM logic, converting the error
signal to a duty cycle to drive the external MOSFETs.
In the ZL6100, the compensation zeros are set by configuring
the FC0 and FC1 pins or via the I
the user has calculated the required settings. This method
eliminates the inaccuracies due to the component tolerances
associated with using external resistors and capacitors
required with traditional analog controllers. Utilizing the loop
compensation settings shown in Table 19 will yield a
conservative crossover frequency at a fixed fraction of the
switching frequency (f
FIGURE 16. CONTROL LOOP BLOCK DIAGRAM
DPWM
f
f
sw
f
sw
sw
/240 < f
/120 < f
FC0 RANGE
/60 < f
1-D
D
Compensation
SW
n
n
n
< f
< f
< f
/20) and 60° of phase margin.
sw
sw
V
sw
/30
/120
IN
/60
22
2
L
C/SMBus interface once
TABLE 19. PIN-STRAP SETTINGS FOR LOOP COMPENSATION
R
C
C
R
O
FC0 PIN
V
OPEN
HIGH
LOW
OUT
ZL6100
Step 1: Using Equation 32, calculate the resonant frequency
of the LC filter, fn
Step 2: Based on Table 19 determine the FC0 settings.
Step 3: Calculate the ESR zero frequency (f
Equation 33.
Step 4: Based on Table 19 determine the FC1 setting.
Adaptive Compensation
Loop compensation can be a time-consuming process,
forcing the designer to accommodate design trade-offs
related to performance and stability across a wide range of
operating conditions. The ZL6100 offers an adaptive
compensation mode that enables the user to increase the
stability over a wider range of loading conditions by
automatically adapting the loop compensation coefficients
for changes in load current.
Setting the loop compensation coefficients through the
I
to be stored in the device in order to utilize adaptive loop
compensation. This algorithm uses the two sets of
compensation coefficients to determine optimal
compensation settings as the output load changes. Please
refer to Application Note AN2033 for further details on
PMBus commands.
2
f
f
C/SMBus interface allows for a second set of coefficients
n
zesr
=
=
2
π
f
f
f
2
sw
sw
sw
πCRc
/10 > f
/10 > f
/10 > f
FC1 RANGE
1
f
f
f
L
1
zesr
zesr
zesr
Reserved
Reserved
Reserved
×
> f
> f
> f
C
zesr
zesr
zesr
.
sw
sw
sw
> f
> f
> f
/10
/10
/10
sw
sw
sw
/30
/30
/30
ZESR
FC1 PIN
December 15, 2010
OPEN
OPEN
OPEN
HIGH
HIGH
HIGH
LOW
LOW
LOW
) using
(EQ. 32)
(EQ. 33)
FN6876.2

Related parts for ZL6100EVAL1Z