ZL6100EVAL1Z Intersil, ZL6100EVAL1Z Datasheet - Page 28

• Manufacturer Part Number: ZL6100EVAL1Z
• Description: EVAL BOARD USB ZL6100
• Manufacturer: Intersil

Specifications of ZL6100EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To determine the SA0 and SA1 resistor values given an
SMBus address (in decimal), follow the indicated steps to
calculate an index value and then use Table to select the
resistor that corresponds to the calculated index value as
shown in Steps 1 through 5:
Digital-DC Bus
The Digital-DC (DDC) communications bus is used to
communicate between Zilker Labs Digital-DC devices. This
dedicated bus provides the communication channel between
devices for features such as sequencing, fault spreading,
and current sharing. The DDC pin on all Digital-DC devices
in an application should be connected together. A pull-up
resistor is required on the DDC bus in order to guarantee the
rise time as follows:
where R
the bus loading. The pull-up resistor may be tied to VR or to
an external 3.3V or 5V supply as long as this voltage is
present prior to or during device power-up. As rules of
thumb, each device connected to the DDC bus presents
approx 10pF of capacitive loading, and each inch of FR4
PCB trace introduces approx 2pF. The ideal design will use a
central pull-up resistor that is well-matched to the total load
capacitance. In power module applications, the user should
consider whether to place the pull-up resistor on the module
or on the PCB of the end application. The minimum pull-up
resistance should be limited to a value that enables any
device to assert the bus to a voltage that will ensure a logic 0
(typically 0.8V at the device monitoring point) given the
pull-up voltage (5V if tied to VR) and the pull-down current
capability of the ZL6100 (nominally 4mA).
Phase Spreading
When multiple point of load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices start to switch
simultaneously. Setting each converter to start its switching
cycle at a different point in time can dramatically reduce
input capacitance requirements and efficiency losses. Since
the peak current drawn from the input supply is effectively
spread out over a period of time, the peak current drawn at
any given moment is reduced and the power losses
proportional to the I
Rise time
1. Calculate SA1 Index:
2. Round the result down to the nearest whole number.
3. Select the value of R1 from Table using the SA1 Index
4. Calculate SA0 Index:
5. Select the value of R0 from Table 24 using the SA0 Index
rounded value from Step 2.
value from Step 4.
SA1 Index = Address (in decimal) ÷ 25
SA0 Index = Address – (25 x SA1 Index)
PU
=
is the DDC bus pull-up resistance and C
R
PU
•
C
RMS
LOAD
2
are reduced dramatically.
≈
1μs
28
LOAD
(EQ. 39)
is
ZL6100
In order to enable phase spreading, all converters must be
synchronized to the same switching clock. The CFG pin is
used to set the configuration of the SYNC pin for each
device as described in section “Switching Frequency and
PLL” on page 15.
Selecting the phase offset for the device is accomplished by
selecting a device address according to Equation 40:
For example:
• A device address of 0x00 or 0x20 would configure no
• A device address of 0x01 or 0x21 would configure 45° of
• A device address of 0x02 or 0x22 would configure 90° of
The phase offset of each device may also be set to any
value between 0° and 360° in 22.5° increments via the
I
further details.
Output Sequencing
A group of Digital-DC devices may be configured to power
up in a predetermined sequence. This feature is especially
useful when powering advanced processors, FPGAs, and
ASICs that require one supply to reach its operating voltage
prior to another supply reaching its operating voltage in order
to avoid latch-up from occurring. Multi-device sequencing
can be achieved by configuring each device through the
I
autonomous sequencing mode.
Autonomous sequencing mode configures sequencing by
using events transmitted between devices over the DDC
bus. This mode is not available on current sharing rails.
The sequencing order is determined using each device’s
SMBus address. Using autonomous sequencing mode
(configured using the CFG pin), the devices must be
assigned sequential SMBus addresses with no missing
addresses in the chain. This mode will also constrain each
device to have a phase offset according to its SMBus
address as described in section “Phase Spreading” on
page 28”.
The sequencing group will turn on in order starting with the
device with the lowest SMBus address and will continue
through to turn on each device in the address chain until all
devices connected have been turned on. When turning off,
the device with the highest SMBus address will turn off first
followed in reverse order by the other devices in the group.
Sequencing is configured by connecting a resistor from the
CFG pin to ground as described in Table 25. The CFG pin is
also used to set the configuration of the SYNC pin as well as
to determine the sequencing method and order. Please refer
Phase offset
2
2
C/SMBus interface. Refer to Application Note AN2033 for
C/SMBus interface or by using Zilker Labs patented
phase offset
phase offset
phase offset
=
device address x 45°
December 15, 2010
(EQ. 40)
FN6876.2