PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 13

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.4
3.4.1
Flash memory write and erase operations are controlled
by the NVMCON register. Programming is performed by
setting NVMCON to select the type of erase operation
(Table 3-2) or write operation (Table 3-3) and initiating
the programming by setting the WR control bit
(NVMCON<15>).
In ICSP mode, all programming operations are
self-timed. There is an internal delay between the user
setting the WR control bit and the automatic clearing of
the WR control bit when the programming operation
is complete. Please refer to Section 7.0 “AC/DC
Characteristics and Timing Requirements” for
information about the delays associated with various
programming operations.
TABLE 3-2:
TABLE 3-3:
3.4.2
The WR bit (NVMCON<15>) is used to start an erase or
write cycle. Setting the WR bit initiates the programming
cycle.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
has been completed. Starting a programming cycle is
performed as follows:
© 2009 Microchip Technology Inc.
NVMCON
NVMCON
4003h
4001h
404Fh
Value
4042h
Value
BSET
Flash Memory Programming in
ICSP Mode
PROGRAMMING OPERATIONS
STARTING AND STOPPING A
PROGRAMMING CYCLE
Write a single instruction word.
Program 1 row (64 instruction words) of
code memory or executive memory.
Erase all code memory, executive
memory and Configuration registers
(does not erase Unit ID or Device ID
registers).
Erase a page of code memory or
executive memory.
NVMCON, #WR
NVMCON ERASE
OPERATIONS
NVMCON WRITE
OPERATIONS
Erase Operation
Write Operation
3.5
The procedure for erasing program memory (all of code
memory, data memory, executive memory and
code-protect bits) consists of setting NVMCON to
404Fh and executing the programming cycle.
A Chip Erase can erase all of user memory. A Table
Write instruction should be executed prior to perform-
ing the Chip Erase to ensure the Chip Erase occurs
correctly.
The Table Write instruction is executed:
• If the TBLPAG register points to user space (is
• If the TBLPAG register points to configuration
Figure 3-5 displays the ICSP programming process for
performing a Chip Erase. This process includes the
ICSP command code, which must be transmitted (for
each instruction), LSb first, using the PGCx and PGDx
pins (see Figure 3-2).
FIGURE 3-5:
PIC24FJ64GA1/GB0
less than 0x80), the Chip Erase will erase only
user memory and Flash Configuration Words.
space (is greater than or equal to 0x80), the Chip
Erase is not allowed. The configuration space can
be erased one page at a time.
Note:
Note:
Erasing Program Memory
The Chip Erase is not allowed when the
TBLPAG points to the configuration space
to avoid the Diagnostic and Calibration
Words from getting erased.
Program memory must be erased before
writing any data to program memory.
Write 404Fh to NVMCON SFR
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
CHIP ERASE FLOW
Done
Start
DS39934B-page 13