PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 9

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.0
ICSP mode is a special programming protocol that
allows you to read and write to the memory of
PIC24FJ64GA1/GB0 devices. The ICSP mode is the
most direct method used to program the device; note,
however, that Enhanced ICSP is faster. ICSP mode
also has the ability to read the contents of executive
memory to determine if the programming executive is
present. This capability is accomplished by applying
control codes and instructions, serially to the device,
using pins PGCx and PGDx.
In ICSP mode, the system clock is taken from the
PGCx pin, regardless of the device’s oscillator Config-
uration bits. All instructions are shifted serially into an
internal buffer, then loaded into the Instruction Register
(IR) and executed. No program fetching occurs from
internal memory. Instructions are fed in 24 bits at a
time. PGDx is used to shift data in and PGCx is used
as both the serial shift clock and the CPU execution
clock.
3.1
Figure 3-1 shows the high-level overview of the
programming process. After entering ICSP mode, the
first action is to Chip Erase the device. Next, the code
memory is programmed, followed by the device
Configuration registers. Code memory (including the
Configuration registers) is then verified to ensure that
programming was successful. Then, program the
code-protect Configuration bits, if required.
© 2009 Microchip Technology Inc.
Note:
DEVICE PROGRAMMING – ICSP
Overview of the Programming
Process
During ICSP operation, the operating
frequency of PGCx must not exceed
10 MHz.
FIGURE 3-1:
3.2
Upon entry into ICSP mode, the CPU is Idle. Execution
of the CPU is governed by an internal state machine. A
4-bit control code is clocked in using PGCx and PGDx,
and this control code is used to command the CPU (see
Table 3-1).
The SIX control code is used to send instructions to the
CPU for execution and the REGOUT control code is
used to read data out of the device via the VISI register.
TABLE 3-1:
0000
0001
0010-1111
Control Code
PIC24FJ64GA1/GB0
4-Bit
ICSP Operation
Program Configuration Bits
Verify Configuration Bits
Mnemonic
REGOUT Shift out the VISI (0784h)
CPU CONTROL CODES IN
ICSP™ MODE
Program Memory
Verify Program
SIX
N/A
Enter ICSP™
Perform Chip
HIGH-LEVEL ICSP™
PROGRAMMING FLOW
Exit ICSP
Erase
Done
Start
Shift in 24-bit instruction
and execute.
register.
Reserved.
Description
DS39934B-page 9