PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 15

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.6
The procedure for writing code memory is the same as
the procedure for writing the Configuration registers,
except that 64 instruction words are programmed at a
time. To facilitate this operation, working registers,
W0:W5, are used as temporary holding registers for the
data to be programmed.
Table 3-5 shows the ICSP programming details, includ-
ing the serial pattern with the ICSP command code
which must be transmitted, Least Significant bit first,
using the PGCx and PGDx pins (see Figure 3-2).
In Step 1, the Reset vector is exited. In Step 2, the
NVMCON register is initialized for programming a full
row of code memory. In Step 3, the 24-bit starting
destination address for programming is loaded into the
TBLPAG register and W7 register. (The upper byte of
the starting destination address is stored in TBLPAG
and the lower 16 bits of the destination address are
stored in W7.)
To minimize the programming time, a packed instruction
format is used (Figure 3-6).
In Step 4, four packed instruction words are stored in
working registers, W0:W5, using the MOV instruction,
and the Read Pointer, W6, is initialized. The contents of
W0:W5 (holding the packed instruction word data) are
shown in Figure 3-6.
TABLE 3-5:
© 2009 Microchip Technology Inc.
Step 1: Exit the Reset vector.
Step 2: Set the NVMCON to program 64 instruction words.
Step 3: Initialize the Write Pointer (W7) for TBLWT instruction.
Step 4: Load W0:W5 with the next 4 instruction words to program.
Command
(Binary)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Writing Code Memory
SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY
000000
040200
000000
24001A
883B0A
200xx0
880190
2xxxx7
2xxxx0
2xxxx1
2xxxx2
2xxxx3
2xxxx4
2xxxx5
(Hex)
Data
NOP
GOTO
NOP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
0x200
#0x4001, W10
W10, NVMCON
#<DestinationAddress23:16>, W0
W0, TBLPAG
#<DestinationAddress15:0>, W7
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
#<LSW2>, W3
#<MSB3:MSB2>, W4
#<LSW3>, W5
In Step 5, eight TBLWT instructions are used to copy the
data from W0:W5 to the write latches of code memory.
Since code memory is programmed 64 instruction
words at a time, Steps 4 and 5 are repeated 16 times to
load all the write latches (Step 6).
After the write latches are loaded, programming is
initiated by writing to the NVMCON register in Steps 7
and 8. In Step 9, the internal PC is reset to 200h. This
is a precautionary measure to prevent the PC from
incrementing into unimplemented memory when large
devices are being programmed. Lastly, in Step 10,
Steps 3-9 are repeated until all of code memory is
programmed.
FIGURE 3-6:
W0
W1
W2
W3
W4
W5
PIC24FJ64GA1/GB0
Description
15
MSB1
MSB3
PACKED INSTRUCTION
WORDS IN W0:W5
LSW0
LSW1
LSW2
LSW3
8 7
DS39934B-page 15
MSB0
MSB2
0