ST62T62CB6 STMicroelectronics, ST62T62CB6 Datasheet - Page 43

• Manufacturer Part Number: ST62T62CB6
• Description: 8BIT MCU OTP 2K+EEPROM, 62T62, DIP
• Manufacturer: STMicroelectronics

Specifications of ST62T62CB6

• Controller Family/series: ST6
• No. Of I/o's: 9
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 1836B
• Oscillator Type: External Only
• Processor Series: ST62T6x
• Core: ST6
• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Data Ram Size: 128 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 9
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-16
• Development Tools By Supplier: ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: Details

TIMER (Cont’d)
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
4.2.4 Timer Registers
Timer Status Control Register (TSCR)
Address: 0D4h — Read/Write
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit
must be cleared by user software before starting a
new count.
Bit 6 = ETI: Enable Timer Interrup
When set, enables the timer interrupt request
(vector #4). If ETI=0 the timer interrupt is disabled.
If ETI=1 and TMZ=1 an interrupt request is gener-
ated.
Bit 5 = D5: Reserved
Must be set to “1”.
Bit 4 = D4
Do not care.
Bit 3 = PSI: Prescaler Initialize Bit
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
TMZ
7
ETI
D5
D4
PSI
PS2
PS1
PS0
0
PSI=“0” both counter and prescaler are not run-
ning.
Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
lect. These bits select the division ratio of the pres-
caler register.
Table 13. Prescaler Division Factors
Timer Counter Register (TCR)
Address: 0D3h — Read/Write
Bit 7-0 = D7-D0: Counter Bits.
Prescaler Register PSC
Address: 0D2h — Read/Write
Bit 7 = D7: Always read as "0".
Bit 6-0 = D6-D0: Prescaler Bits.
D7
D7
7
7
PS2
0
0
0
0
1
1
1
1
D6
D6
D5
D5
ST62T52C ST62T62C/E62C
PS1
1
0
0
1
1
0
0
1
D4
D4
D3
D3
PS0
1
0
1
0
1
0
1
0
D2
D2
Divided by
D1
D1
128
16
32
64
8
1
2
4
43/78
D0
D0
0
0