PIC18F4420T-I/PT Microchip Technology, PIC18F4420T-I/PT Datasheet - Page 10

• Manufacturer Part Number: PIC18F4420T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4420T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2XXX/4XXX FAMILY
In addition to the code memory space, there are three
blocks that are accessible to the user through Table
Reads and Table Writes. Their locations in the memory
map are shown in
Users may store identification information (ID) in eight ID
registers. These ID registers are mapped in addresses,
200000h through 200007h. The ID locations read out
normally, even after code protection is applied.
Locations, 300000h through 30000Dh, are reserved for
the Configuration bits. These bits select various device
options and are described in
tion
normally, even after code protection.
Locations, 3FFFFEh and 3FFFFFh, are reserved for
the Device ID bits. These bits may be used by the
programmer to identify what device type is being
programmed and are described in
figuration
normally, even after code protection.
FIGURE 2-9:
DS39622L-page 10
Note:
1FFFFFh
2FFFFFh
3FFFFFh
01FFFFh
000000h
Word”. These Configuration bits read out
Word”. These Device ID bits read out
Sizes of memory areas are not to scale.
Unimplemented
Code Memory
Configuration
Read as ‘0’
Figure
and ID
Space
CONFIGURATION AND ID LOCATIONS FOR PIC18F2XXX/4XXX FAMILY DEVICES
2-9.
Section 5.0 “Configura-
Section 5.0 “Con-
2.3.1
Memory in the address space, 0000000h to 3FFFFFh,
is addressed via the Table Pointer register, which is
comprised of three pointer registers:
• TBLPTRU at RAM address 0FF8h
• TBLPTRH at RAM address 0FF7h
• TBLPTRL at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.
Addr[21:16]
TBLPTRU
MEMORY ADDRESS POINTER
ID Location 1
ID Location 2
ID Location 3
ID Location 4
ID Location 5
ID Location 6
ID Location 7
ID Location 8
CONFIG1H
CONFIG2H
CONFIG3H
CONFIG4H
CONFIG5H
CONFIG6H
CONFIG7H
CONFIG1L
CONFIG2L
CONFIG3L
CONFIG4L
CONFIG5L
CONFIG6L
CONFIG7L
Device ID1
Device ID2
Addr[15:8]
TBLPTRH
 2010 Microchip Technology Inc.
3FFFFEh
3FFFFFh
30000Ah
30000Bh
30000Ch
30000Dh
200000h
200001h
200002h
200003h
200004h
200005h
200006h
200007h
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
300008h
300009h
TBLPTRL
Addr[7:0]